在深次微米VLSI的時代，已可將各種應用系統做於晶片之內，其中將包括ASIC、處理器與軟體、以及硬體模組等組成，在系統設計時，要選擇各應用功能以何種形式在系統晶片內執行，這種選擇稱之為軟硬體分割。不同的軟硬體分割影響到所能達成之晶片設計的整體成本與效能。
在此研究中，我們對一基於合成的軟硬分割之估算方法做理論與軟體設計的研究探討，針對下列幾個部分分別剖析：
•軟體排程
•軟硬體協同排程
•軟硬體分割的成本與效能估算
對於一個系統敘述當給定一選擇的軟硬體分割與資源分配時，既可以產生其系統成本與效能的評量，提供系統設計者或軟硬體分割最佳化軟體使用。
我們根據這幾個部分所探討出的方法，設計相對應的實驗軟體，進行設計實例的實驗。

In the age of deep submicron VLSI, we can design various system applications in a single chip. On this system-on-chip design, there are ASIC circuitry, processor core together with software components, and hardware modules. During system design, we need to select the forms of execution for kinds of system functions.It is called hardware/software partitioning. Different hardware/software partitioning, affect the achievable cost and performance of the accordingly elaborated system chip designs.
In this research, we explore research and software design issues of an estimation method for hardware/software partitioning. It consists of these tasks:
•software scheduling
•hardware/software co-scheduling
•cost and performance estimation for
hardware/software partitioning
For a system description, given a chosen hardware/software partitioning and a set of allocated resources, we can perform the corresponding cost and performance estimation task that can be utilized directly by system designs or can be called by a hardware/software partitioning optimization program. We designed the experimental software for this estimation method. We also carried out a set of experiments based upon real and synthesized design cases.

第 一 章 導論　………………………………………………………………………………… 1
1. 1 研究動機　……………………………………………………………………………… 1
1. 2 相關研究　……………………………………………………………………………… 2
1. 2. 1 協同合成與分割　………………………………………………………………………2
1. 2. 2 排程　………………………………………………………………………3
1. 2. 3 控制資料流程圖　…………………………………………………………3
1. 3 研究目的　……………………………………………………………………………… 5
1. 4 論文架構　……………………………………………………………………………… 5

第 二 章 軟硬體協同設計方法　……………………………………………………………… 6
2. 1 組織架構與系統流程　……………………………………………………………… 6
2. 1. 1 組織架構　………………………………………………………………………………6
2. 1. 2 系統流程　………………………………………………………………………………7
2. 2 軟體排程　………………………………………………………………………………10
2. 2. 1 產生軟體排程下各資料的生存時段　………………………………… 10
2. 2. 2 產生軟體排程　………………………………………………………… 12
2. 2. 3 多處理器之軟體排程　………………………………………………… 14
2. 3 軟硬體協同排程　………………………………………………………………………15
2. 3. 1 基本硬體模組排程　…………………………………………………………………15
2. 3. 2 產生巨集硬體模組排程　……………………………………………………………16
2. 3. 3 軟硬體協同排程　……………………………………………………………………16
2. 3. 4 排程法則　……………………………………………………………… 19
2. 4軟硬體分割的成本與效能計算　……………………………………………………… 21

第 三 章 實驗規劃　……………………………………………………………………………23
3. 1 軟體設計系統流程　……………………………………………………………………23
3. 2 系統設計敘述格式　……………………………………………………………………24
3. 3 模擬軟體簡介　…………………………………………………………………………27
3. 4 實驗規劃　………………………………………………………………………………28
3. 5 實驗結果與討論　………………………………………………………………………35

第 四 章 結 論　………………………………………………………………………………44

參 考 文 獻　……………………………………………………………………………………45

[1]Tsung Lee, A Cost/Performance Estimation Method for Hardware/Software Partitioning, Tech. Rep. No.01-03, VLSI CAD Lab. Dept. of Electrical Eng., Nat’l Sun Yat-Sen Univ., Kao-Hsiung, Taiwan, R.O.C. July 2001
[2]Beaty, S.J. "List scheduling: alone, with foresight, and with lookahead," Proceedings of the First International Conference on Massively Parallel Computing Systems, 1994 Page(s): 343 –347
[3]Ernst, R., Henkel, J., Benner, T., "Hardware-software cosynthesis for microcontrollers," IEEE Design & Test of Computers , Volume: 10 Issue: 4 , Dec. 1993 Page(s): 64 -75
[4]Giovanni De Micheli , Synthesis and Optimization of Digital
Circuits, McGraw-Hill, 1994
[5]Gupta, R.K.; De Micheli, G., "Hardware-software cosynthesis for digital systems," IEEE Design & Test of Computers , Volume: 10 Issue: 3 , Sept. 1993 Page(s): 29 -41
[6]Hidalgo, J.I.; Lanchares, J. "Functional partitioning for hardware-software codesign using genetic algorithms," Proceedings of the 23rd EUROMICRO Conference , 1997 Page(s): 631 -638
[7]de Jong, G.G. "Data flow graphs_system specification with the most unrestricted semantics," Proceedings of the European Conference on Design Automation. Conf., 1991 Page(s): 401 –405
[8]Kim, K.; Karri, R.; Potkonjak, M., “Micro-preemption synthesis: an enabling mechanism for multi-task VLSI systems,” 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997 Page(s): 33 –38
[9]King-Yin Cheung, T.; Hellestrand, G.; Kanthamanon, P., “A transformational codesign methodology,” Proceedings of the ASP-DAC '97 , 1997 Page(s): 299 -305
[10]Kurt Mehlhorn, Stefan Näher, LEDA A Platform for Combinatorial and Geometric Computing
[11]Mahesh C. Gupta, Yash P. Gupta and Anup Kumar , "Genetic
Algorithm Application in a Machine Scheduling Problem," Proceedings of the 1993 ACM conference on Computer science, 1993, Pages 372 - 377
[12]Parameswaran, S., “HW-SW co-synthesis: the present and the future,” Proceedings of the ASP-DAC'98. 1998, Page(s): 19 -22
[13]Saha, D.; Mitra, R.S.; Basu, A., "Hardware software partitioning using genetic algorithm," Proceedings. of the Tenth International Conference on VLSI Design, 1997., 1997 Page(s): 155 -160
[14]Srinivasan, V.; Radhakrishnan, S.; Vemuri, R. , "Hardware Software Partitioning with Integrated Hardware Design Space Exploration," Proceedings Design, Automation and Test in Europe, 1998 Page(s): 28 -35