由於半導體技術持續地進步，使得一種結合處理邏輯�處理器與高密度記憶體的新系統單晶片計算機結構能順利發展，此類計算機結構一般稱為記憶體處理器或智慧型記憶體，其在高效能計算時，能有效降低處理器與記憶體之間的效能差距。這種架構結合了不同的處理器於單一系統內，而這些處理器，則可依他們的計算能力與記憶體存取之效能與耗能的不同加以分類。我們主要針對兩個問題加以探討：如何增進程式在記憶體處理器架構的執行效能；如何降低程式在記憶體處理器架構執行時所消耗的能量。因而需要發展一套新的策略以了解各種處理器之不同效能並且將工作分配給最適合的處理器以充分發揮其能力。有鑑於此，這份研究提出了一個新的原始碼對原始碼的自動平行化系統，稱為SAGE，來發揮記憶體處理器架構的優點。有別於傳統以輪次為基本的平行化系統，SAGE採用以陳述為基本的分析方法：將程式依陳述分解成多個區塊，並針對主處理器與記憶體處理器，產生適合的執行計畫表。SAGE系統整合了陳述分割、權重評估、效能排程、與耗能降低排程，自動地轉換Fortran原始程式，以增進程式在記憶體處理器架構下之執行效能或減少其能量消耗。這份論文詳細地說明這些分析方法，並以經由SAGE轉換後之真實的測速程式在記憶體處理器架構下執行之實驗結果，討論SAGE系統與這些分析方法之效能。

Continuous improvements in semiconductor fabrication density are enabling new classes of System-on-a-Chip (SoC) architectures that combine extensive processing logic/processing with high-density memory. Such architectures are generally called Processor-in-Memory or Intelligent Memory and can support high-performance computing by reducing the performance gap between the processor and the memory. This architecture combines various processors in a single system. These processors are characterized by their computational and memory-access capabilities in performance and energy consumption. Two main problems addressed here are how to improve the performance and reduce the energy consumption of applications running on Processor-in-Memory architectures. Accordingly, a novel strategy must be developed to identify the capabilities of the different processors and dispatch the most appropriate jobs to them to exploit them fully. Accordingly, this study proposes a novel automatic source-to-source parallelizing system, called SAGE, to exploit the advantages of Processor-in-Memory architectures. Unlike conventional iteration-based parallelizing systems, SAGE adopts statement-based analytical approaches. The strategy of the SAGE system, which decomposes the original program into blocks and produces a feasible execution schedule for the host and memory processors, is also investigated. Hence, several techniques including statement splitting, weight evaluation, performance scheduling and energy reduction scheduling are designed and integrated into the SAGE system to automatically transform Fortran source programs to improve the performance of the program or reduce energy consumed by the program executed on Processor-in-Memory architecture. This thesis provides detailed techniques and discusses the experimental results of real benchmarks which are transformed by SAGE system and targeted on the Processor-in-Memory architecture.

Acknowledgement ii
摘要 iii
Abstract iv
Table of Contents v
List of Tables vii
List of Figures viii
Chapter 1 Introduction 1
Chapter 2 Related Work 4
2.1 PIM Architectural Aspects 4
2.2 PIM Compiler Aspect 6
2.3 Weight Evaluation Aspects 7
2.4 Scheduling Aspects 8
2.5 Energy Reduction Aspects 9
Chapter 3 Processor-in-Memory Architecture 11
3.1 Architecture Description 11
3.2 Synchronization Mechanism 13
3.3 Cache Coherence Mechanism 14
Chapter 4 Methodology 15
4.1 Statement Splitting and WPG
Construction 18
4.2 Weight Evaluation 22
4.2.1 Partial Profiling Weight Evaluation
Mechanism 23
4.2.2 Self-Patch Weight Evaluation 27
4.3 Performance Scheduling Mechanisms for
One-P.Host and One-P.Mem Configuration 31
4.3.1 Basic Scheduling Mechanism 31
4.3.2 Seesaw Dispatching Mechanism 33
4.4 Performance Scheduling Mechanism for
One-P.Host and Many-P.Mems
Configuration 39
4.5 Optimizing Techniques 51
4.5.1 Tiling for PIM 51
4.5.2 Loop splitting for PIM 55
4.5.3 IMOP recognition 57
4.6. Energy Reduction Scheduling for
PIM Architectures 61
4.6.1 Performance-Oriented Energy
Reduction Scheduling 62
4.6.2 Energy-Oriented Energy Reduction
Scheduling 67
4.6.3 Example 71
4.7 Implementation of the SAGE system 73
Chapter 5 Experimental Results 75
5.1 Experimental Results of the Scheduling
Mechanism for the One-P.Host and
One-P.Mem Configuration 76
5.2 Experimental Results of the Scheduling
Mechanism for the One-P.Host and
Many-P.Mem Configuration 79
5.3 Experimental Results of the Energy
Reduction Scheduling Mechanism for
the One-P.Host and One-P.Mem
Configuration 82
Chapter 6 Conclusion 84
References 86
Vita 92

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