本文是針對覆晶球柵陣列(FCBGA)封裝體，搭配無芯基板(Coreless substrate)技術，藉由改變基板介電材料特性、結構厚度與佈銅率，以提升封裝體與基板的可靠度，使封裝體因為熱膨脹係數不匹配所造成的翹曲現象，進而導致封裝體失效的機率大為降低。
本文分為實驗量測與數值模擬兩種方式，來分析覆晶球柵陣列封裝體在溫度負載下所產生的翹曲現象。在實驗部分使用陰影雲紋法(Shadow Moiré)來量測封裝體於溫度負載作用下，各封裝製程結束後降溫至室溫的翹曲數據，並比較不同的介電材料特性對翹曲值的影響趨勢。而數值模擬則是利用有限元素分析軟體ANSYS，檢視封裝體和純基板在溫度負載下之翹曲值，再與實驗數據相互驗證。最後進行介電材料特性、結構厚度與佈銅率之參數化分析，求得各參數因子的影響顯著程度，並提出優化封裝體與基板翹曲現象之建議方案。
藉由實驗數據與模擬驗證的結果顯示，基板介電材料只採用介電材料A的封裝體其翹曲表現較差。由封裝體等效模型的材料分析結果顯示，選擇熱膨脹係數越小、楊氏係數越大、玻璃轉化溫度越低的介電材料可以降低封裝體的翹曲值，其貢獻度分別為22%、13.5%與18%；而在結構分析方面，改善封裝體翹曲值的影響因子為銅線層厚度與介電材料層厚度，其貢獻度分別為30%、1.5%，顯示銅線層厚度較介電材料層厚度相比具有高顯著性。
由基板細線路模型分析結果得知，改善基板翹曲值的影響因子為晶片端介電材料層厚度、晶片端銅線層厚度、植球端介電材料層厚度與植球端銅線層厚度，在貢獻度方面則是植球端銅線層厚度達18%，其餘層面的貢獻度極不顯著。至於佈銅率分析方面，較佳的佈銅比例為晶片端銅線層51%的佈銅率、植球端銅線層32%的佈銅率，在影響力部分，晶片端銅線層的佈銅率其影響力較植球端銅線層的佈銅率為顯著。

The thesis aims to enhance the reliability of the flip-chip ball grid array (FCBGA) package and coreless substrate by changing the material properties of dielectric material, thickness and copper coverage. The probability of failure of the package owing to warpage because of CTE mismatch is then significantly reduced.
The warpage of a FCBGA package under thermal loadings through both experiment and simulation is investigated. Shadow Moiré was applied to assess the warpage of a package at room temperature after finishing each assembly process. And we compared the influence of dielectric material, thickness and copper coverage on warpage of the package. Utilizing the finite element software ANSYS to build up models under thermal loadings we received the warpage of package and bare substrate and verified the results with experimental data to identify the significant degree for various factors.
The experimental data and numerical simulation results show the warpage of the package only applied dielectric material A in the substrate is not good. From the material analysis of the equivalent package model, we can decrease the warpage if we choose lower CTE, higher modulus and lower Tg of dielectric material, and their contributions are 22%, 13.5% and 18%, respectively. From the structure analysis of the equivalent package model, we find out the factor of improving warpage of package is the thickness of copper trace and the thickness of dielectric material, and their contributions are 30% and 1.5%, respectively. It shows the thickness of copper trace is more significant than that of dielectric material.
From the results of detailed bare substrate model, it is obvious to see that the factors of improving warpage of substrate are the thickness of dielectric material at chip side, the thickness of copper trace at chip side, the thickness of dielectric material at ball side and the thickness of copper trace at ball side. The contribution of the thickness of copper trace at ball side is 30% and the contributions of other layers are not significant. As for the analysis of copper coverage, it is better to find that copper coverage is 51% on the copper trace layer at chip side, 32% on the copper trace layer at ball side. And the influence of the copper coverage of copper trace layer at chip side is more outstanding than that of copper trace layer at ball side.

論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 v
圖次 vii
表次 x
第一章 緒論 1
1-1 前言 1
1-2 IC封裝介紹 1
1-2-1 封裝的技術層級、目的與步驟 1
1-2-2 球柵陣列封裝(Ball Grid Array, BGA)簡介 2
1-2-3 覆晶封裝介紹 2
1-2-4 無芯基板(Coreless substrate)技術概述 3
1-3 研究動機與目的 4
1-4 文獻回顧 5
1-5 組織與章節 6
第二章 理論與數值解析 10
2-1 有限元素分析概論 10
2-2 線性分析理論 10
2-3 非線性分析理論 11
2-4 材料特性分析 13
2-4-1 雙線性動態硬化塑性(Bilinear Kinematic Hardening Plasticity) 14
2-4-2 潛變(Creep) 15
第三章 實驗與數值模擬方法 19
3-1 陰影雲紋法(Shadow Moiré) 19
3-1-1 陰影雲紋法簡介 19
3-1-2 陰影雲紋法之原理[40-41] 19
3-1-3 陰影雲紋法之相位移(Phase Shift)原理[42] 19
3-2 實驗儀器介紹 21
3-3 實驗步驟 21
3-4 ANSYS數值模擬 22
3-4-1 基本假設 22
3-4-2 ANSYS模擬流程 22
3-5 分析參數規劃 24
3-5-1 封裝體等效模型翹曲值分析參數設定 25
3-5-2 基板細線路模型翹曲值分析參數設定 25
第四章 數值模擬結果 42
4-1 陰影雲紋干涉實驗(Shadow Moiré) 42
4-2 數值模擬分析驗證 42
4-3 參數化分析 43
4-3-1 封裝體等效模型翹曲值分析 43
4-3-2 基板細線路模型結構分析 44
4-3-3 基板細線路模型佈銅率分析 45
第五章 分析與討論 71
5-1 封裝體等效模型翹曲值分析 71
5-2 基板細線路模型結構分析 72
5-3 基板細線路模型佈銅率分析 73
第六章 結論 78
參考文獻 80

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