首先，本論文提出一低成本之電漿顯示器資料分配器用於增加影像畫質。在定址與顯示分離技術之下，使用10個子畫面並將資料重新分配，使得我們的設計得以降低20%的電漿顯示器資料分配器成本，並且解決了動態假輪廓線的問題。

其次，我們提出一個用於類神經網路之關聯性記憶體的雙極性數值內積乘法器，設計用來計算兩個雙極性數值的內積。從我們的分析當中，可以發現本內積乘法器的延遲比先前的設計改進許多，從O(2n) 降到 O(n)。

此外，我們亦針對P+離子植入之唯讀記憶體提出3維位址解碼架構，使得其相對應的資料單元可以用自然排列方式編碼與儲存。不只是其面積可以縮小，包含存取時間以及功率消耗都減少很多。因此，其非常適合用於植入式元件。

最後，我們介紹一多種參數之神經介面微電刺激器系統，其包含了外部控制模組、傳輸規格與系統單晶片。在這個系統當中，主要是完成外部所給予的指令去電刺激相對應的神經。另一方面，未來其可以感測並傳輸相對應的神經訊號給外部的監測儀器。

In this thesis, we firstly present a low-cost plasma display panel (PDP) data dispatcher for image enhancement. By taking advantage of the proposed ADS method with 10 subfields and data reordering, our design can reduce 20% of the PDP dispatcher cost and resolve the “dynamic false contour” problem.

Secondly, a bipolar-valued inner product processor for associative memory neural networks is proposed to compute the inner product of two bipolar-valued vectors. Our analysis shows that the delay of inner product is reduced significantly from O(2n) to O(n).

We also propose a 3-dimensional address decoding structure associated with a corresponding data cell encoding arrangement for P+implant ROMs such that the data words are encoded and stored in the ROMs in a natural pattern. Not only is the size of the entire decoder shrunk, the access time and power dissipation is also greatly reduced, which is very suitable to be utilized in implantable devices.

Finally, we introduce a multi-parameter implantable neural interface micro-stimulator system, including the external control module, the protocol, and the SOC (system-on-chip) chip. The proposed system is expected to carry out the externally given commands to stimulate the corresponding neural trunks. On the other way around, it can sense and deliver the response of the neural trunks to an external monitoring device in the future.

1 Introduction 1
1.1 Motivation ...................................... 1
1.2 Related Prior Works ................................ 2
1.2.1 Plasma display panel data dispatcher ................... 2
1.2.2 Neural computation and bio-medical chip design ............. 2
1.3 Organization of the Dissertation .......................... 5
2 A Low-cost Plasma Display Panel Data Dispatcher for Image Enhancement 6
2.1 Principle of Plasma Display Panel ......................... 6
2.1.1 Method for driving plasma display panel ................. 8
2.1.2 Address display separated driving method ................ 9
2.1.3 Dynamic false contours ........................... 11
2.2 Plasma Display Panel Data Dispatcher ...................... 12
2.2.1 Input data format .............................. 13
2.2.2 Average picture level (APL) module ................... 15
2.2.3 8-to-10 sub-field translator ......................... 17
2.2.4 Control module ............................... 17
2.2.5 SRAM module ............................... 18
2.2.6 High-voltage data driver IC ........................ 20
2.2.7 Output buff'er ................................ 22
2.2.8 High-voltage control signal generator ................... 22
2.3 Comparison and Implementation ......................... 23
2.3.1 PDP dispatcher accomplishment ...................... 23
2.4 Summary . ..................................... 25
3 A Fast Bipolar-valued lamer Product Processor 29
3.1 Associative Memory Networks ........................... 29
3.2 High-speed Bipolar-valued Vector Inner Product Processor ........... 31
3.2.1 Inner product term generator ....................... 32
3.2.2 (2n - 1)-to-n compressor unit ....................... 33
3.2.2.1 basic 3-2 compressor building block ............... 34
3.2.2.2 framework of (2n - 1)-to-n compressor ............. 34
3.2.3 Bipolar-to-binary converter ........................ 36
3.2.4 Inner product adjustment unit ....................... 37
3.3 Performance Analysis ................................ 38
3.3.1 Chip implementation and measurement .................. 39
3.3.2 Physical chip testing ............................ 40
3.4 Summary ...................................... 41
4 An Area-saving Decoder Structure for ROMs 43
4.1 Area-saving Decoder for ROMs .......................... 43
4.1.1 Strnetures of ROMs ............................ 43
4.1.2 1-dimensional decoder strncture of ROMs ................ 44
4.1.3 2-dimensional decoder strncture ...................... 44
4.1.4 3-dimensional decoder strncture ...................... 47
4.1.5 Performance analysis ............................ 49
4.1.5.1 transistor count .......................... 49
4.1.5.2 speed analysis .......................... 53
4.1.6 Chip implementation: 256~8 ROM .................... 53
4.2 Simulation and Testing ............................... 54
4.2.1 Speed (Delay) simulation .......................... 54
4.2.2 Power dissipation simulations ....................... 57
4.2.3 Physical chip testing ............................ 57
4.3 Summary ...................................... 57
5 Multi-parameter Neural Interface Micro-stimulator System 60
5.1 The Architecture of Neural Interface Micro-stimulator System ......... 60
5.1.1 Magnetic flux and inductance ....................... 61
5.1.2 Mutual inductance ............................. 62
5.1.3 Class-E amplifier .............................. 64
5.1.4 Internal power receiver ........................... 66
5.2 Multi-parameter Micro-stimulator Chip ...................... 67
5.2.1 Power regulator ............................... 68
5.2.2 On-chip C-less ASK demodulator ..................... 69
5.2.3 Packet format ................................ 72
5.2.4 Baseband schematic design ......................... 75
5.2.4.1 built-in clock generator ..................... 76
5.2.4.2 built-in reset and FSM ...................... 73
5.2.4.3 data and clock recoveW ..................... 78
5.2.4.4 serial to parallel converter .................... 79
5.2.4.5 decoder .............................. 80
5.2.4.6 DAC (digital-to-analog converter) ................ 81
5.3 Simulation and Testing ............................... 81
5.3.1 On-chip regulator .............................. 81
5.3.2 On-chip C-less ASK demodulator ..................... 82
5.3.3 Multi-parameter micro-stimulator chip .................. 83
5.4 Summary ..................................... 84
6 Conclusions and Future Works 88
6.1 Conclusions ..................................... 88
6.2 Future Works .................................... 89
Bibliography 90

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