在本篇論文，我們提出有效率面積之先進加密標準處理器之設計，透過應用四種新的共同子表示式消去法，實現先進加密標準中不同轉換的子功能。子功能的第一種類型衍生於結合每一個先進加密標準的回合中相鄰的轉換。子功能的第二種類型衍生於整合在先進加密標準的加密和解密流程理的轉換並共用共同的運算。我們提出的位元階層的共同子表示式消去法，透過抽取子功能表示式的共同項部分，進一步地減少實現子功能的面積花費。為了檢驗每項技術的有效性，本論文仔細分析以上所提的結合和整合轉換的方式及使用共同子表示式消去法所造成的面積減少效應。經由標準元件庫實際合成的結果，在先進加密標準上使用我們所提出的共同子表示式消去法，其面積減少的比率與Synopsys的最佳化簡結果相比，有明顯的改善。

In this dissertation, we propose area-efficient Advanced Encryption Standard (AES) processor designs by applying four new common-subexpression-elimination (CSE) algorithms to the sub-functions that realize the various transformations in AES encryption and decryption. The first category of sub-functions is derived by combining adjacent transformations in each AES round into a new transformation. The other category of sub-functions is from the integrated transformations in the AES encryption and decryption process with shared common operations. Then the proposed bit-level CSE algorithm reduces further the area cost of realizing the sub-functions by extracting the common factors in the bit-level expressions of these sub-functions. The separate area-reduction effects of combinations, integrations and CSE optimization mentioned above are analyzed in order to examine the efficiency of each technique. Cell-based implementation results show that the area reduction rates of the AES processors with our proposed CSE methods achieve significant area improvement compared with Synopsys optimization results.

Chapter 1 Introduction
1.1 Motivation
1.2 Overall AES algorithm
1.3 Four Major Transformations
Chapter 2 Previous AES Design Methods
2.1 SB/ISB Realizations
2.2 MC/IMC Realizations
2.3 Realizations of Combined SB/SR/MC and IMC/ISR/ISB Units
2.4 Realizations of KE Unit
Chapter 3 Two Proposed Substructure Sharing Methods for XOR-based Operations
3.1 Proposed Method I: Bit-level Substructure Sharing
3.1.1 Algorithm Description
3.1.2 Example for MC
3.2 Proposed Method II: Both Byte-level and Bit-level Substructure Sharing
3.2.1 Algorithm Description
3.2.2 Example for IMC
Chapter 4 Two Proposed CSE Algorithms for Sum-of-Product Operations
4.1 Proposed Method III: Vertical CSE Algorithm
4.1.1 Algorithm Description
4.1.2 Example for IMC
4.2 Proposed Method IV: Horizontal CSE Algorithm
4.2.1 Algorithm Description
4.2.2 Example for MI in GF(24)
Chapter 5 Comparisons and Implementations
5.1 Comparison of SB/ISB and MC/IMC Implementations
5.1.1 Comparison of SB/ISB Implementations
5.1.2 Comparison of MC/IMC Implementations
5.2 Overall AES System Implementation
5.2.1 Three Various AES Architectures
5.2.2 Experimental Results of AES Implementation
5.2.3 Measurement Data of AES Chip
Chapter 6 Conclusions and Future Works
Bibliography

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