現今電子裝置為了達到高效能、低成本以及低耗電，採用系統晶片是一趨勢，隨著更多功能與效能的需求，先進的矽統晶片有更多的矽智產被整合到單一晶片中。然而發展這種複雜的系統晶片挑戰性很高，因為現今系統晶片基於成本考量，只有有限的輸入輸出接腳可供系統除錯用，限制了晶片內部系統狀態的觀測能見度。為了解決這問題，我們提出了SYS-SIP，以協助系統晶片之驗證、除錯、觀測與效能調校。SYS-SIP包含五個基礎建設模組：微處理器外部中斷驗證器、嵌入式仿真器、微處理器追蹤器、匯流排追蹤器、以及協定檢查器，每個模組在驗證、除錯、觀測、以及效能調校上都扮演獨特的功能。我們已經將SYS-SIP應用在三維圖形系統晶片上的發展，實驗結果顯示本SYS-SIP有效的幫助系統晶片之發展，並大幅度的縮短系統晶片之發展時程。

System-on-a-Chip (SoC) is a trend to achieve high performance, low cost, and low power in modern electronic devices. As the demand of functionality and performance increase, more IPs (Intellectual Property) are integrated into a modern SoC. Developing such a complex SoC is challenging since the SoC has limited observability; modern SoCs usually leave limited spared I/O pins for debugging purpose due to cost consideration, making it hard to analyze the internal activities via the limited I/O pins. This hampers the SoC development. To ease the difficulty, we have implemented the SYS-SIP (National Sun Yat-Sen university's SoC Infrastructure IP's) to enable the SoC development in terms of verification, debugging, monitor
ing, and performance tuning. The SYS-SIP consists of five members: Processor External Interrupt Verification Module (PEVM), ICE, processor tracer, bus tracer, and protocol checker. Each of them serves specific purposes in verification, debugging, monitoring, and performance tuning. The SYS-SIP can be applied at diffierent design stages: RTL, FPGA, and chip level. The results show that SYS-SIP eases the SoC development and shortens the time-to-market significantly.

1 Introduction 1
1.1 Motivation 1
1.2 Proposed solution 2
2 Related works 5
2.1 Processor External Interrupt Verification 5
2.1.1 Unit-level verification 7
2.1.2 System-level verification 8
2.2 Trace-based Debugging 9
2.2.1 Lossy and Lossless compression 10
2.2.2 Problems in Traditional Trace Compression Algorithms: Pre-T tracing 12
3 Infrastructure IP 15
3.1 SYS-SIP 15
3.2 Processor External Interrupt Verification Module 15
3.3 ICE 17
3.4 Processor Tracer 18
3.5 Bus Tracer 19
3.6 Bus Protocol checker 20
3.7 Cooperation among the SYS-SIP members 21
3.7.1 PEVM + Processor Tracer 22
3.7.2 ICE + Bus Tracer 22
3.7.3 Bus protocol checker + Bus Tracer 23
4 Processor External Interrupt Verification Module (PEVM) 24
4.1 PEVM Generation Flow 24
4.1.1 Frame work overview 24
4.1.2 Verification model 27
4.1.3 Interrupt Behavior Verification Scenario Database 31
4.1.4 Verification Environment - Memory bus 33
4.1.5 Verification Environment - On-chip bus 36
4.2 Exception description language (EXPDL) 39
4.3 Verification case generation and result production 42
4.3.1 Individual interrupt 42
4.3.2 Intra-instruction multiple interrupt 43
4.3.3 Nested interrupt 46
5 Pre-T/Post-T bus tracer 49
5.1 The basic reverse compression formulation 49
5.2 On-chip bus tracer hardware architecture 50
5.2.1 DiRerential compression 51
5.2.2 Slice compression 53
5.2.3 Dictionary-based compression 54
5.3 Circular buRer management 56
6 Experimental results 60
6.1 Deployment in SoC chip: the 3D Graphics SoC Chip 60
6.1.1 PEVM 60
6.1.2 ICE 72
6.1.3 Bus Tracer 72
6.1.4 Bus Protocol Checker 78
6.1.5 Preliminary 3D Graphics SoC Chip 80
6.2 Bridging the ESL and physical SoC environment 81
6.3 Enhancing bus related monitoring/debugging activities in a FPGA Development Tool 83
7 Conclusion 84
8 Future work 85
Bibliography 88
A EXPDL User Guide 1
A.1 Operation Section 1
A.1.1 MICRO ARCHITECTURE Section 1
A.1.2 SYNTAX GROUP Section 3
A.1.3 GROUP CYCLE Section 4
A.2 Exception Section 6
A.3 Pipeline Section 8
B PEVM User Guide 12
B.1 Memory layout of generated software 12
B.2 Read in EXPDL 17
B.3 Generate verification hardware and software 23
B.4 Module Connection 27
B.4.1 Interrupt activator organization in the memory bus environment 27
B.4.2 Interrupt activator organization in the on-chip bus environment 27
B.4.3 Simulation and Debugging 32

[1] A. P. Su and K.-J. Lee, "Date'07 trip report, 3rd meeting of 2007, esl working group," in Taiwan SoC Consortium, June 2007.
[2] A. Deshpande, "Verification of IP-core based SoC's," in Proceedings of the 9th International Symposium on Quality Electronic Design, 2008.
[3] F.-C. Yang, W.-K. Huang, and I.-J. Huang, "Automatic verification of external interrupt behaviors for microprocessor design," in Proceedings of the 44th Design Automation Conference (DAC), June 4-8, 2007, pp. 896-901.
[4] F.-C. Yang, W.-K. Huang, J.-K. Zhong, and I.-J. Huang, "Automatic verification of external interrupt behaviors for microprocessor design," IEEE Trans. Computer-Aided Design, vol. 27, no. 9, pp. 1670-1683, 2008.
[5] F.-C. Yang, J.-K. Zhong, and I.-J. Huang, "Verifying external interrupts of embedded microprocessor in SoC with on-chip bus," in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2008), Nov. 2008, pp. 372-377.
[6] I.-J. Huang, C.-F. Kao, H.-M. Chen, C.-N. Juan, and T.-A. Lu, "A retargetable embedded in-circuit emulation module for microprocessors," IEEE Des. Test. Comput., vol. 19, no. 4, pp. 28-38, July-Aug. 2002.
[7] C.-F. Kao, S.-M. Huang, and I.-J. Huang, "A hardware approach to real-time program trace compression for embedded processors," IEEE Trans. Circuits Syst. I, vol. 54, no. 3, pp. 530-543, Mar. 2007.
[8] C.-F. Kao, I.-J. Huang, and C.-H. Lin, "An embedded multi-resolution AMBA trace analyzer for microprocessor-based SoC integration," in Proceedings of the ACM/IEEE Design Automation Conference (DAC'07), 2007.
[9] Y.-T. Lin, W.-C. Shiue, and I.-J. Huang, "A multi-resolution AHB bus tracer for read-time compression of forward/backward traces in a curcular buRer," in Proceedings of Design Automation Conference (DAC), July 2008, pp. 862-865.
[10] Y.-T. Lin, C.-C. Wang, , and I.-J. Huang, "AMBA AHB bus protocol checker with e±cient debugging mechanism," in Proceedings of the IEEE International Symposium on Circuits and Systems, Seattle, Washington, USA, May 18-21 2008.
[11] "Practical approaches to SoC verification," White Paper, Verisity Design Systems, 2000.
[12] ARM, AMBA Specification (Rev 2.0) ARM IHI0011A, May 1999.
[13] AMBA AXI Protocol Specification, May 2004.
[14] M. Bose, M. H. Nodine, A. Chodavadia, W. R. J. Jr, L. R. Nunes, and V. Zavadsky, "Modeling IP responses in testcase generation for systems-on-chip verification," in Proceedings of the Fourth International Workshop on Microprocessor Test and Verification (MTV'03), May 29-30, 2003, pp. 7-10.
[15] M. Srivas and M. Bickford, "Formal verification of a pipelined microprocessor,"IEEE Softw., vol. 7, no. 5, pp. 52-64, Sept. 1990.
[16] P. Windley, "Formal modeling and verification for microprocessor," IEEE Trans. Comput., vol. 44, no. 1, pp. 54-72, Jan. 1995.
[17] W. Hunt and J. Sawada, "Verifying the FM9801 microarchitecture," IEEE Micro, vol. 19, no. 3, pp. 47-55, May/June 1999.
[18] J. Sawada, W. A., and J. Hunt, "Processor verification with precise exceptions and speculative execution," in proceeding of 10th International Computer Aided Verification Conference, vol. 1427, Mar. 23-26, 1998, pp. 135-146.
[19] M. N. Velev, "Formal verification of VLIW microprocessors with speculative execution," in proceedings of Computer Aided Verification 2000, July 2000, pp. 296-311.
[20] I. Wagner, V. Bertacco, and T. Austin, "Stresstest: an automatic approach to test generation via activity monitors," in Proceedings of the 42nd IEEE Design Automation Conference (DAC), June 2005, pp. 783-788.
[21] A. Adir, H. Azatchi, E. Bin, O. Peled, and K. Shoikhet, "A generic micro-architecture test plan approach for microprocessor verification," in Proceedings of the 33rd IEEE Design Automation Conference (DAC), June 2005, pp. 769-774.
[22] T. Li, D. Zhu, L. Liang, Y. Guo, and S. Li, "Automatic function test program generation for microprocessor verification," in Proceedings of IEEE International Conference on Asia and South Pacific Design Automation Conference (ASP-DAC) 2005, vol. 2, Jan. 2005, pp. 1039-1042.
[23] F. Corno, G. Cumani, M. S. Reorda, and G. Squillero, "Evolutionary test program induction for microprocessor design verification," in Proceedings of the 11th IEEE International Conference on Asian Test Symposium (ATS), Nov. 2002, pp. 368-373.
[24] J.-S. Yim, C.-J. Park, W.-S. Yang, H.-S. Oh, H.-C. Lee, H. Choi, T.-H. Kim, S.-J. Lee, N. Won, Y.-H. Lee, I.-C. Park, and C.-M. Kyung, "Verification methodology of compatible microprocessor," in Proceedings of IEEE International Conference on Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 1997, pp. 173-180.
[25] J. An, X. Fan, S. Zhang, D. Wang, and Y. Wang, "Vmsim: Virtual machine based a full system simulation platform for microprocessor's functional verification," in Proceedings of International Conference on Information Technology-New Generations, Apr. 2006, pp. 245-249.
[26] S. Mehta, S. Ahmed, S. Al-Ashari, D. Chen, D. Chen, S. Cokmez, P. Desai, R. Eltejaein, P. Fu, J. Gee, T. Granvold, A. Iyer, K. Lin, G. Maturana, D. McConn, H. Mohammed, J. Mostoufi, A. Moudgal, S. Nori, N. Parveen, G. Peterson, M. Splain, and T. Yu, "Verification of the UltraSPARCtm micro-processor," in Proceedings of IEEE International Conference on Compcon '95, Mar. 1995, pp. 451-461.
[27] J. Monaco, D. Holloway, and R. Raina, "Functional verification methodology for the PowerPC 604 microprocessor," in Proceedings of 33rd IEEE Design Automation Conference, June 1996, pp. 319-324.
[28] J. Yu, T. Li, and Q. Tan, "The use of uml sequence diagram for system-on-chip system level transaction-based functional verification," in Proceedings of the Sixth World Congress on Intelligent Control and Automation (WCICA), June 21-23, 2006, pp. 6173-6177.
[29] A. Cheng, A. Cheng, and C.-C. Lim, "A software test program generator for verifying system-on-chips," in Proceedings of the 10th IEEE International High-Level Design Validation and Test Workshop, Nov. 30 -Dec. 2, 2005, pp. 79-86.
[30] S.-H. Lee, J.-G. Lee, S. Kim, W. Hwangbo, and C.-M. Kyung, "SoC design environment with automated configurable bus generation for rapid prototyping," in Proceedings of 6th International Conference On ASIC (ASICON), Oct. 24-27, 2005, pp. 41-45.
[31] Y. Nakamura, K. Hosokawa, I. Kuroda, K. Yoshikawa, and T. Yoshimura, "A fast hardware/software co-verification method for System-On-a-Chip by using a C/C++ simulator and FPGA emulator with shared register communication,"in Proceedings of the 41th Design Automation Conference (DAC), June 7-11, 2004, pp. 299-304.
[32] IEEE, IEEE standards 1149.1, 1990.
[33] H. Packard, Concepts of Emulation And Analysis, Edition 1, Nov. 1990.
[34] H. Neugass, "Approaches to on-chip debugging," Computer Design, Tech. Rep., Dec. 1998.
[35] T. Williams, "On-chip debug support gets to the heart of code," Embedded Systems Development, Tech. Rep. 1, Jan. 2000.
[36] J.-S. Yang and N. A. Touba, "Expanding trace buRer observation window for in-system silicon debug through selective capture," in Proceedings of the IEEE 26th VLSI Test Symposium, Apr. 27-May 1 2008, pp. 345-351.
[37] E. Anis and N. Nicolici, "Low cost debug architecture using lossy compression for silicon debug," in Proceedings of the IEEE Design, Automation & Test in Europe Conference, Apr. 16-20 2007, pp. 1-6.
[38] SignalTap Embedded Logic Analyzer Megafunction, Altera, 2001. [Online]. Available: http://www.altera.com/literature/ds/dssignal.pdf
[39] Embedded Trace Macrocell Architecture Specification, ARM Ltd., Feb. 2006.
[40] E. Rotenberg, S. Bennett, and J. E. Smith, "A trace cache microarchitecture and evaluation," IEEE Trans. Comput., vol. 48, pp. 111-120, Feb. 1999.
[41] ARM. AMBA AHB Trace Macrocell (HTM) Technical Reference Manual ARM DDI 0328D, ARM Ltd., 2007.
[42] E. Anis and N. Nicolici, "On using lossless compression of debug data in embedded logic analysis," in Proceedings of the IEEE International Test Conference, Oct. 21-26 2007, pp. 1-10.
[43] W.-J. Huang, N. Saxena, and E. J. McCluskey, "A reliable LZ data compressor on reconfigurable coprocessors," in Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines, 2000, pp. 249-259.
[44] J. Ziv and A. Lempel, "A universal algorithm for sequential data compression," IEEE Trans. Inform. Theory, vol. IT-23, pp. 337-343, May 1977.
[45] T. A. Welch, "A technique for high-performance data compression," IEEE Trans. Comput., pp. 8-19, 1984.
[46] E. E. Johnson, J. Ha, and M. B. Zaidi, "Lossless trace compression," IEEE Trans. Comput., vol. 50, pp. 158-173, Feb. 2001.
[47] A. B. Hopkins and K. D. McDonald-Maier, "Debug support strategy for systems-on-chips with multiple processor cores," IEEE Trans. Comput., vol. 55, pp. 174-184, Feb. 2006.
[48] 34 Channel LA1034 Logicport Logic Analyzer, Intronix, 2005. [Online]. Available: http://www.pctestinstruments.com/
[49] J. Gaisler, E. Catovic, M. Isomaki, K. Glembo, and S. Habinc, GRLIB IP Core User's Manual, Gaisler Research. [Online]. Available: http: //www.gaisler.com/products/grlib/grlib.html
[50] TLA5000B Series Logic Analyzers, Tektronix, 2003. [Online]. Available: http://www2.tek.com/
[51] S. P. Whalen, "Apparatus and method for circular buRering on an on-chip discontinuity trace," US Patent 6,243,836, 2001.
[52] D. P. Mann, "Debug interface including a compact trace record storage," US Patent 6,094,729, 2000.
[53] The Nexus 5001 Forum Standard for a Global Embedded Processor Debug Interface, IEEE-ISTO 5001, IEEE/ Industry Standards and Technology Organization, 1999. [Online]. Available: http://www.nexus5001.org/
[54] DesignWare AHB Verification IP Databook, 4th ed., Synopsys Ltd., Feb. 2007.
[55] High speed USB-powered Ant Logic Analyzers, RockyLogic, 2002. [Online]. Available: http://www.rockylogic.com/
[56] Logic Analyzer LAP-A, Zeroplus, 2006. [Online]. Available: http://www.zeroplus.com.tw/logic-analyzern en/products.php
[57] C.-H. Cheng, M.-G. Chen, T.-C. Huang, and C.-F. Tzu, "Logic analyzer data processing method," US Patent 7,392,434, 2004.
[58] D. A. Edwards and A. W. Rich, "Circuit for storing trace information," US Patent 6,615,370, 2003.
[59] R. Thekkath, "Dynamic selection of a compression algorithm for trace data," US Patent 7,069,544, 2006.
[60] P. Mishra and N. Dutt, "Architecture description languages for programmable embedded systems," IEEE Micro, vol. 152, pp. 285-297, May 2005.
[61] A. Meyer, Principle of functional verification. Nwenes, 2003.
[62] ARM7TDMI Data Sheet, Advanced RISC Machines Ltd, 1995.
[63] G. Research, The LEON-2 User's Manual, June 2002. [Online]. Available: http://www.gaisler.com/
[64] PIC16C63A/65B/73B/74B Data Sheet, Microchip Technology Inc., 2000.
[65] TransEDA, "Vn-cover." [Online]. Available: http://www.transeda.com/products/vn-cover/details.php
[66] Y.-T. Lin and I.-J. Huang, "Enhanced 32-bit microprocessor-based soc for energy efficient mp3 decoding in portable devices," in Proceedings of IEEE International Conference on Comsumer Electronics (CE), Jan. 2007, pp. 1-2.
[67] ARM, AHB CPU Wrappers Technical Reference Manual, 2001.
[68] AHB Example AMBA SYstem Technical Reference Manual, ARM, 1999.
[69] E. M, S. Kumar, G. Potdar, and P. Game, "Approach for debugging in a single session gdb," in Proceedings of the International Conference on Information and Communication Technology in Electrical Sciences (ICTES 2007), Dec. 2007, pp. 1043 - 1046.
[70] J.-H. Ji, G. Woo, H.-B. Park, and J.-S. Park, "Design and implementation of retargetable software debugger based on gdb," in Proceedings of the Third International Conference on Convergence and Hybrid Information Technology, Nov. 2008, pp. 737-740.
[71] X. Liu and Q. Xu, "On reusing test access mechanisms for debug data transfer in SoC post-silicon validation," in Proceedings of the 17th Asian Test Symposium, Nov. 2008, pp. 24 - 27.
[72] H. Yi, S. Park, and S. Kundu, "A design-for-debug (dfd) for noc-based SoC debugging via noc," in Proceedings of the 17th Asian Test Symposium, Nov. 2008, pp. 289-294.
[73] B. Vermeulen and K. Goossens, "A network-on-chip monitoring infrastructure for communication-centric debug of embedded multi-processor SoCs," in Proceedings of the International Symposium onVLSI Design, Automation and Test, Apr. 2009, pp. 183-186.
[74] P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-oRs for network-on-chip interconnect architectures," IEEE Trans. Comput., vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
[75] C. Hochberger and A. Weiss, "Acquiring an exhaustive, continuous and realtime trace from socs," in Proceedings of IEEE International Conference on Computer Design, Oct. 2008, pp. 356 - 362.
[76] A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau, "Expression: a language for architecture exploration through compiler/simulator retargetability," in Proceedings of IEEE International Conference on Design, Automation and Test in Europe, Mar. 1999, pp. 485-490.
[77] P. Mishra and N. Dutt, "A methodology for validation of microprocessors using equivalence checking," in Proceedings of 4th International Workshop on the Microprocessor Test and Verification: Common Challenges and Solutions, May 2003, pp. 83-88.