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論文名稱 Title |
多參數可植入式微電刺激系統之設計與實作 Design and Implementation of A Multi-parameter Implantable Micro-stimulator System |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
91 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2008-10-09 |
繳交日期 Date of Submission |
2008-10-14 |
關鍵字 Keywords |
植入式、微電刺激、解調變器、體外實驗 in vitro, demodulator, micro-stimulation, implantable |
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統計 Statistics |
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中文摘要 |
本論文提出一多參數可植入式微電刺激系統,係使用無線傳輸多參數控制,可避免傷口感染,更可產生多種刺激波形來符合不同的生醫應用。另外,亦設計一電腦圖形化介面來搭配微電刺激系統,讓使用更為方便。此微電刺激系統也已進行活體外實驗,可成功刺激神經細胞。 此外,為了降低傳統的ASK解調變器中的電容所帶來的系統面積負擔,本論文亦提出一無電容的ASK解調變器,使用偏壓電路為基礎的包跡線偵測電路(envelope detector)搭配一史密特觸發器來進行解調變。另外,藉由改善包跡線偵測電路的電度雜訊容限(noise margin)而設計出一全MOS的ASK解調變器,可進ㄧ步縮小系統面積。 除此之外,提出二種高敏感度電壓對頻率轉換器,以配合全雙工之設計。利用一電壓對電流轉換電路,一充放電電路和一全MOS電壓窗型比較器VWC1,完成一高敏感度的電壓對頻率轉換器VFC1。另外,設計一快速之全MOS電壓窗型比較器VWC2,以提昇VFC2之線性度。 最後,本論文提出一大範圍的輸出輸入單元,做為植入式微電刺激系統對外的傳輸介面。利用堆疊式PMOS與NMOS當做輸出級,搭配一動態閘極偏壓產生電路,可以傳送以及接收不同高低電壓的訊號,同時可避免閘極過壓以及漏電流的問題。 |
Abstract |
This thesis proposes a multi-parameter implantable micro-stimulator system. By using wireless communication and the muli-parameter control, the infection caused by the wound could be avoided and various stimulation waveforms could be generated for different bio-medical applications. Besides, a graphic user interface (GUI) is implemented for the proposed micro-stimulator for the convenience of usage. Moreover, the in vitro experiments are carried out, where the neurons could be stimulated successfully. To reduce the system area caused by external capacitors required by traditional ASK demodulators, a C-less ASK demodulator is proposed in this thesis. A bias-based envelope detector and a Schmitt trigger are used for demodulation. Moreover, by enlarging the noise margin of the envelope detector, an all-MOS ASK demodulator is carried out such that no passive element is needed and the system area could be further reduced. Besides, two high sensitivity voltage-to-frequency (VFC) are proposed for the full duplex transmission. By using a voltage-to-current converter, a charge and discharge circuit, and an all-MOS voltage window comparator 1 (VWC1), a high sensitivity VFC1 is accomplished. Moreover, a linear VFC2 is also proposed by including a fast all-MOS voltage window comparator, VWC2. Finally, a wide range I/O buffer is proposed for the interface of the implantable micro-stimulator system. With the stacked PMOS and NMOS output stage and the dynamic gate bias generator, high voltage and low voltage signals (VDDH and VDDL) could be transmitted and received without any gate-oxide overstress and leakage currents. |
目次 Table of Contents |
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv 1 Introduction 1 1.1 Motivation and Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.2.1 Implantable micro-stimulator system . . . . . . . . . . . . . . . . . . . 3 1.2.2 ASK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.3 Voltage-to-frequency converter . . . . . . . . . . . . . . . . . . . . . . . 5 1.2.4 Wide-range I/O buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Multi-parameter Implantable Micro-stimulator System 9 2.1 Multi-parameter Micro-stimulator System . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.2 Wireless transmitter and receiver . . . . . . . . . . . . . . . . . . . . . 11 2.2 SOC Design of the Multi-parameter Micro-stimulator . . . . . . . . . . . . . . 12 2.2.1 Power and the regulator . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 On-chip C-less ASK demodulator . . . . . . . . . . . . . . . . . . . . . 14 2.2.3 Baseband schematic design . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.3 Measurement and in vitro Experiment . . . . . . . . . . . . . . . . . . . . . . 17 2.3.1 GUI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.3.2 Class-E transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3.3 Micro-stimulator SOC chip . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.3.4 in vitro experiment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3 Miniaturized ASK Demodulator without Resistor and Capacitor 24 3.1 C-less ASK demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.2 Simulation and Measurement of C-less ASK Demodulator . . . . . . . . . . . . 28 3.3 All-MOS ASK Demodulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.1 Prior bias-based C-less ASK demodulator . . . . . . . . . . . . . . . . 29 3.3.2 Circuitry of the all-MOS ASK demodulator . . . . . . . . . . . . . . . 31 3.4 Simulation and Measurement Results of All-MOS ASK Demodulator . . . . . 34 3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4 Voltage-to-Frequency Converter With High Sensitivity Using An All-MOS Voltage Window Comparator 39 4.1 All-CMOS Voltage-to-Frequency Converter . . . . . . . . . . . . . . . . . . . . 39 4.1.1 Architecture of the proposed VFC . . . . . . . . . . . . . . . . . . . . . 40 4.1.2 Schematic design of VFC . . . . . . . . . . . . . . . . . . . . . . . . . . 40 4.1.3 All-MOS voltage-to-current converter . . . . . . . . . . . . . . . . . . . 41 4.2 All-MOS Voltage Window Comparator 1 (VWC1) . . . . . . . . . . . . . . . . 42 4.3 Implementation and Measurement of VFC1 . . . . . . . . . . . . . . . . . . . 43 4.4 All-MOS Voltage Window Comparator 2 (VWC2) . . . . . . . . . . . . . . . . 46 4.4.1 Linearity analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 4.4.2 Schematic design of VWC2 . . . . . . . . . . . . . . . . . . . . . . . . . 47 4.5 Implementation and Measurement of VFC2 . . . . . . . . . . . . . . . . . . . 48 4.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5 Wide-Range 5.0/3.3/1.8 V I/O Buffer 53 5.1 Wide-Range 5.0/3.3/1.8 V I/O Buffer . . . . . . . . . . . . . . . . . . . . . . . 53 5.2 Implementation and Measurement . . . . . . . . . . . . . . . . . . . . . . . . . 58 5.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 6 Conclusions and Future Works 65 6.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Bibliography 68 |
參考文獻 References |
[1] M. A. Abdeen and M. A. Stuchly, “Modeling of magnetic field stimulation of bent neu- rons,” IEEE Trans. on Biomedical Engineering, vol. 41, no. 11, pp. 1092-1095, Dec. 1994. [2] J. H. Blaise, R. J. Austin-Lafrance, and J. D. Bronzino, “Development of inhibitory and facilitatory modulation in the rat dentate gyrus,” in Proc. of the 1996 IEEE Twenty- Second Annual Northeast Bioengineering Conf., pp. 89-90, Mar. 1996. [3] J. R. Buitenweg, W. L. C. Rutten, and E. Marani, “Geometry based dynamic modeling of neuron-electrode interface,” in Proc. of 22nd Inter. Conf. on EMBS, pp. 2004-2007, Jul. 2000. [4] R. E. Isaacs, D. J. Weber, and A. B. Schwartz, “Work toward real-time control of a cortical neural prosthesis,” IEEE Trans. on Rehabilation Engineering, vol. 8, no. 2, pp. 196-198, June 2000. [5] C. C. McIntyre and W. M. Grill, “Microstimulation of spinal mononeurons : a model study,” in Proc. of 19th Inter. Conf. on EMBS, pp. 2032-2034, Oct. 1997. [6] W. A. Waugaman and C. B. Schrader, “Optimal current model from surface electrodes,” in Proc. of the 33rd Conf. on Decision and Control, pp. 4112-4113, Dec. 1994. [7] J. S. Walter, J. S. Wheeler, W. Cai, W. W. King, and R. D. Wurster, “Evaluation of a suture electrode for direct bladder stimulation in a lower motor neuron lesioned animal mode,” IEEE Trans. on Rehabilation Engineering, vol. 7, no. 2, pp. 159-166, June 1999. [8] G. E. Loeb, F. J. R. Richmond, D. Olney, T. Cameron, A. C. Dupont, K. Kood, R. A. Peck, P. R. Troyk, and H. Schulman, “BIONTM Bionic neurons for functional and ther- apeutic electrical stimulation,” 20th IEEE Engineering in Medicine and Biology Society, vol. 5, pp. 2305-2309, Nov. 1998. [9] T. Eken and K. Gundersen, “Electrical stimulation resembling normal motor-unit activ- ity: effects on denervated fast and slow rat muscles,” J. of Physiol., vol. 402, no. 1 pp. 651-669, Aug. 1988. [10] C. Bohotin, M. Scholsem, S. Multon, D. Martin, V. Bohotin, and J. Schoenen, “Vagus nerve stimulation in awake rats reduces formalin-induced nociceptive behaviour and fos- immunoreactivity in trigeminal nucleus caudalis, ” J. of Pain, vol. 101, no. 1-2, pp. 3-12, Jan. 2003. [11] C. H. Seif, P. M. Braun, S. Bross, J. Scheepe, J. Weiss, S. Schumacher, S. Zendler, P. Alken, and K. P. Junemann, “Selective block of urethral sphincter contraction using a modified Brindley electrode in sacral anterior root stimulation of the dog,” Neurourol Urodyn, vol. 21, no. 5, pp. 502-10, 2002. [12] E. Ganio, A. R. Luc, G. Clerico, and M. Trompetto, “Sacral nerve stimulation for treat- ment of fecal incontinence: a novel approach for intractable fecal incontinence,” Dis Colon Rectum, vol. 44, no. 5, pp. 619-629, May 2001. [13] S. Salmons, G. T. Gunning, I. Taylor, S. R. Grainger, D. J. Hitchings, J. Blackhurst, and J. C. Jarvis, “Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture,” Med. Eng. Phys., vol. 23, no. 1, pp. 37-43, Jan. 2001. [14] K. Arabi and M. A. Sawan, “Electronic design of a multichannel programmable implant for neuromuscular electrical stimulation,” IEEE Trans. on Rehabilation Engineering, vol. 7, no. 2, pp. 204-214, June 1997. [15] B. Ziaie, M. D. Nardin, A. R. Coghlan, and K. Najafi, “A single-channel implantable microstimulator for functional neuromuscular stimulation,” IEEE Trans. on Biomedical Engineering, vol. 44, no. 10 pp. 909-920, Oct. 1997. [16] J. A. Von Arx and K. Najafi, “A wireless single-chip telemetry-powered neural stimulation system,” in Proc. of IEEE Inter. Solid-State Circuits Conf., pp. 214-215, Feb. 1999. [17] J. C. Lin, “Computer methods for field intensity predictions, ” in Handbook of Biological Effects of Electromagnetic Fields, C. Polk and E. Postow, FL: CRC Press, chap. 2, pp. 273-313, 1986. [18] C. M. Zierhofer and E. S. Hochmair, “High-efficiency coupling-insensitive transcutaneous power and data transmission via an inductive link,” IEEE Trans. on Biomed. Eng., vol. 37, no. 7, pp. 716-722, Jul. 1990. [19] B. Razavi, Design of analog CMOS integrated circuits, New York: McGraw-Hill, pp. 377-380, 2001. [20] R. J. Baker, H. W. Li, and D. E. Boyce, CMOS circuit design, layout, and simulation, 2nd Ed., New York: Wiley-Interscience, 2005. [21] W. Liu, K. Vichienchom, M. Clements, S. C. DeMarco, C. Hughes, E. McGucken, M. S. Humayun, E. De Juan, J. D. Weiland, and R. Greenberg, “A neuro-stimulus chip with telemetry unit for retinal prosthetic device,” IEEE J. of Solid-State Circuits, vol. 35, no. 10, pp. 1487-1497, Oct. 2000. [22] M. Bar′u, H. Valdenegro, C. Rossi, and F. Silveira, “An ASK demodulator in CMOS technology,” in Proc. of IV Iberchip Workshop, pp. 37-42, Mar. 1998. [23] H. Yu and K. Najafi, “Low-power interface circuit for bio-implantable microsystems,” in Proc. of 2003 IEEE Inter. Solid-States Circuits Conf., vol. 1, pp. 194-203, Feb. 2003. [24] A. Djemouai and M. Sawan, “New CMOS current-mode amplitude shift keying demodu- lator (ASKD) dedicated for implantable electronic devices,” in Proc. of 2004 IEEE Inter. Symp. on Circuits and Systems (ISCAS 2004), vol. 1, no. 1, pp. 441-444, May 2004. [25] R. Harjani, O. Birkenes, and J. Kim, “An IF stage design for an ASK-based wireless telemetry system,” in Proc. of 2000 IEEE Inter. Symp. on Circuits and Systems (ISCAS 2000), vol. 1, pp. 52-55, May 2000. [26] G. Gudnason, “A low-power ASK demodulator for inductively coupled implantable elec- tronics,” in Proc. of IEEE Inter. Solid-States Circuits Conf., pp. 385-388, Feb. 2000. [27] M. Sawan, Y. Hu, and J. Coulombe, “Wireless smart implants dedicated to multichannel monitoring and microstimulation,” IEEE Circuits and Systems Magazine, vol. 5, no. 1, pp. 21-39, 2005. [28] H. Yu and R. Bashirullah, “A Low Power ASK Clock and Data Recovery Circuit for Wireless Implantable Electronics,” in Proc. of 2006 IEEE Custom Integrated Circuits Conf., pp. 249-252, Sept. 2006. [29] A. Tekin, M. R. Yuce, J. Shabani, and Wentai Liu, “A low-power FSK modula- tor/demodulator for an MICS band transceiver,” in Proc. of 2006 IEEE Radio and Wire- less Symp., pp. 159-162, Jan. 2006. [30] M. Stork, “New Σ-Δ voltage to frequency converter,” 9th Inter. Conf. on Electronics, Circuits and Systems, vol. 2, pp. 631-634, Sept. 2002. [31] S. Cai and I. M. Filanovsky, “High precision voltage-to-frequency converter,” in Proc. of 1994 IEEE Midwest Symp. on Circuits and Systems, vol. 2, pp. 1141- 1144, Aug. 1994. [32] R. A. Pease, “Amplitude-to-frequency converter,” United States Patent no. 3746968, July 17, 1973. [33] F. N. Trofimenkoff, F. Sabouri, J. Qin, and J. W. Haslett, “A square-rooting voltage-to- frequency converter,” IEEE Trans. on Instrumentation and Measurement, vol. 46, no. 5, pp. 1208-1211, Oct. 1997. [34] H. Matsumoto and K. Waranabe, “Switched-capacitor frequency-to-voltage and voltage- to-frequency converters based on charge-balancing principle,” in Proc. of 1988 IEEE Inter. Symp. on Circuits and Systems (ISCAS 1988), vol. 3, pp. 2221-2224, June 1988. [35] P. E. Allen and D. R. Holberg, CMOS analog circuit design, layout, and simulation, New York: Oxford, 2002. [36] P. I. Yakimov, E. D. Manolov, and M. H. Hristov. “Design and implementation of a V-f converter using FPAA,” in Proc. of 27th Inter. Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, vol. 1, pp. 126-129, May 2004. [37] C.-H. Chuang and M.-D. Ker, “Design on mixed-voltage-tolerant I/O interface with novel tracking circuits in a 0.13-um CMOS technology,” in Proc. of IEEE Int. Symp. on Circuits and Systems, 2004, vol. 2, pp. 577-580, May 2004. [38] T. Furukawa, D. Turner, S. Mittl, M. Maloney, R. Serafin, W. Clark, L. Longenbach, and J. Howard, “Accelerated gate-oxide breakdown in mixed-voltage I/O buffers, ” in Proc. IEEE Int. Reliability Physics Symp. pp. 169-173, Apr. 1997. [39] A.-J. Annema, G. J. G. M. Geelen, and P. C. de Jong, “5.5-V I/O in a 2.5-V 0.25-μm CMOS technology,”IEEE J. of Solid-state Circuits, vol. 36, no. 3, Mar. 2001. [40] S.-L. Chen and M.-D. Ker, “An output buffer for 3.3-V applications in a 0.13-μm 1/2.5-V CMOS process,” IEEE Trans. on Circuits and Systems-II: Express Brief, vol. 54, no. 1, pp. 14-18, Jan. 2007. [41] E. R. Minami, S. B. Kuusinen, E. Rosenbaum, P. K. Ko, and C. Hu, “Circuit-level simulation of TDDB failure in digital CMOS circuits,” IEEE Trans. on Semiconduct. Manufact. vol. 8, no. 3, pp. 370-374, Aug. 1995. [42] R. Moazzami and C. Hu, “Projecting gate oxide reliability and optimizing reliability screens,” IEEE Trans. on Electron Devices, vol. 37, no. 7, pp. 1643-1650, Jul. 1990. [43] G. P. Singh and P. B. Salem, “High-voltage-tolerant I/O buffers with low-voltage CMOS process,” IEEE J. of Solid-State Circuits, vol. 34, no. 11, pp. 1512-1525, Nov. 1999. [44] M.-D. Ker and F.-L. Hu, “Design on mixed-voltage I/O buffers with consideration of hot- carrier reliability,” Int. Symp. VLSI Design, Auto. and Test, 2007, (VLSI-DAT 2007), pp. 1-4, Apr. 2007. [45] M. J. M. Pelgrom and E. C. Dijkmans, “A 3/5 V compatible I/O buffer,” IEEE J. of Solid-State Circuits, vol. 30, no. 7, pp. 823-825, July 1995. [46] M. Takahashi, T. Sakurai, K. Sawada, K. Nogami, M. Ichida, and K. Matsuda, “3.3 V-5 V compatile I/O circuit without thick gate oxide,” in Proc. of IEEE Custom Integrated Circuits Conf. pp. 23.3.1-23.3.4, 1992. [47] M.-D. Ker and C.-S Tsai, “Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic n-well bias circuit,” in Proc. of IEEE Int. Symp. Circuits and Systems, vol. 5, pp. V-97-V-100, May. 2003. [48] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. on Circuits and Systems I: Regular Papers, vol. 53, no. 9, pp. 1934-1945, Sept. 2006. [49] M.-D. Ker and S.-L. Chen, “Mixed-voltage I/O buffer with dynamic gate-bias circuit to achieve 3×VDD input tolerance by using 1×VDD devices and single VDD supply,” in Proc. of 2005 IEEE Int. Solid-State Circuits Conf., vol. 1, pp. 524-614, Feb. 2005. [50] G. Liu, Y. Wang, and S. Jia, “A new design of mixed-voltage I/O buffers with low- voltage-thin-oxide CMOS process,” in Proc. of Int. Conf. on ASIC, pp. 201-204, Oct. 2007. [51] M.-D. Ker and S.-L. Chen, “Design of mixed-voltage I/O buffer by using NMOS-blocking technique,” IEEE J. of Solid-State Circuits, vol. 41, no. 10, pp. 2324-2333, Oct. 2006. [52] H. Sanchez, J. Siegel, C. Nicoletta, J. P. Nissen, and J. Alvarez, “A versatile 3.3/2.5/1.8- V CMOS I/O driver built in a 0.2-μm, 3.5-nm Tox, 1.8-V CMOS technology,” IEEE J. of Solid-State Circuits, vol. 34, no. 11, pp. 1501-1511, Nov. 1999. |
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