現今嵌入式系統的軟硬體設計已經太過複雜，軟硬體共同驗證(HW/SW co-verification)變得相當困難，以至於新的設計階層－電子系統層級(ESL)逐漸興起。現今的電子系統層級的驗證已經可以做到整個系統晶片的模擬，包含處理器(Processor)、匯流排(Bus)、記憶體(Memory)等硬體，也可以在此系統上執行簡單的程式，但是因為模擬速度的限制使得比較大型的軟體－如作業系統的驗證很難實現。目前已經有人提出作業系統模擬器與硬體模擬語言的共同模擬平台(QEMU-SystemC)，可大幅的加速CPU的模擬速度，但是由於更抽象的CPU行為模擬，所以很難探討整個系統的執行時間與效能。因此本論文提出方法：分別建立CPU、Cache、TLB、SDRAM的Timing Model；把與需要的硬體連接上TLM (Transaction-level modeling)的Bus模組做共同模擬，便可以估算整個系統的執行時間來做效能分析，而且不會導致過大的模擬時間。另外本論文提出了分析程式，可以同時顯示每個程式區塊的執行時間，幫助設計者快速定位軟硬體的效能瓶頸。三維繪圖晶片是本論文的實驗範例，根據本論文提供的效能資訊我們找到了效能的瓶頸。

Nowadays the designs of HW/SW are extremely complex. HW/SW co-verification is really difficult, consequently the new design layer, Electronic-System Level (ESL), is proposed to replace the original design flow. Today’s ESL can verify the whole system simulation include the Processor, Bus, Memory… such as the HWs. It also can run a small program on the system. But it is hard to verify the larger program - such as the operation system because the limitations of the simulation speed. Currently some people proposed the QEMU-SystemC virtual platform. It can greatly speed up the CPU simulation speed. But the abstract simulated CPU has no timing information. It is infeasible to explore the system execution time and performance. We proposed the method: CPU, Cache, TLB and SDRAM with timing model; connect the CPU and the designed HW in TLM bus module in the HW/SW co-simulation. We can analyze the performance in the estimated timing information, and it will not take many simulation times. In addition, we developed the analysis program to show the execution time in each program block. It can help designer to locate the performance bottleneck quickly in the complex HW/SW. A case study is the 3D graphic SoC. We find the performance bottleneck in HW/SW design according the performance information purposed by our work.

Chapter 1. Introduction 1
1.1 Motivation 1
1.2 Background 1
Chapter 2. Related Works 5
2.1 Preliminary Knowledge 5
2.1.1 ESL 5
2.1.2 QEMU 6
2.1.3 SystemC 7
2.1.4 TLM 7
2.1.5 QEMU-SystemC Co-Simulation 7
2.2 Software Performance Analysis 9
2.2.1 Data Analysis Base 9
2.2.2 Simulation Base 9
2.2.3 Physical Platform Base 10
2.3 QEMU timing model 11
Chapter 3. Performance Analysis in QEMU 12
3.1 CPU clock in QEMU 12
3.2 Embedding SystemC in QEMU 13
3.3 CPU Model 16
3.4 Bus model 16
3.5 Cache model 18
3.5.1 Instruction Cache 19
3.5.2 Data Cache 20
3.6 TLB Model 20
3.7 SDRAM Model 22
3.8 Program identification 24
3.9 HW timing model in SystemC 25
3.10 HW clock in SystemC 26
Chapter 4. Analysis Event Trace 27
4.1 Analysis Trace Flow 27
4.2 Analysis Trace Report 29
4.3 Analysis Example 33
Chapter 5. NSYSU 3D Graphic 36
5.1 3D model in OpenGL 36
5.2 3D Rendering Flow 38
5.3 GLSL (OpenGL Shading Language) 41
5.4 NSYSU 3D HW/SW Architecture 42
5.5 NSYSU 3D Execution Flow 43
Chapter 6. Experiment Result 49
6.1 Timing Model Verification 49
6.2 NSYSU 3D Performance Analysis 54
Chapter 7. Conclusion 59
Chapter 8. Future Work 60
References 61
Appendix A. QEMU-SystemC with CoWare 63

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