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博碩士論文 etd-1015113-190908 詳細資訊
Title page for etd-1015113-190908
論文名稱
Title
OpenGL ES2.0 三維圖形加速系統晶片與AXI系統匯流排之整合及驗證方法
SoC Integration and Verification of an AXI-Based 3D Graphics OpenGL ES2.0 SoC
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
173
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-10-25
繳交日期
Date of Submission
2013-11-15
關鍵字
Keywords
匯流排、AXI、AHB、驗證、整合、OpenGL ES2.0
BUS, AXI, AHB, Verification, OpenGL ES2.0, Integration
統計
Statistics
本論文已被瀏覽 5652 次,被下載 585
The thesis/dissertation has been browsed 5652 times, has been downloaded 585 times.
中文摘要
現今,由於晶片製程的進步與IP設計技術的不斷創新與精進,進而使得系統統晶片的設計複雜度大幅提升,伴隨而來的是數量越趨龐大的系統測試樣本,面對如此狀況,如何進行有效率的系統測試,便是一個十分重要的議題。

本論文以我們資工系3DG團隊所設計之3DG OpenGL ES2.0 SoC為例,介紹如何從System Modeling Level至FPGA Emulation Level,使用均一化的機制建立各層級的驗證平台,使測試樣本可Reuse在這些不同層級的平台上,進而省去撰寫個別平台的測試腳本時間,之後更採取自動化驗證機制,來對整體系統進行更有效率的樣本測試及比對結果的正確性,排除人為操作上可能造成的失誤,提升整體系統晶片驗證的可靠性與涵蓋率。

此外,為了提升我們3DG OpenGL ES2.0 SoC的效能,我們將原本所採用的AHB系統匯流排置換為效能更高的AXI系統匯流排,並使用Synopsys旗下的coreConsultant軟體進行相關模組的產生,以節省AXI環境下各模組的開發與驗證時間,在本論文中也將介紹其產生與合成的相關流程。
Abstract
Nowadays, due to improvement of fabrication and IP design technology, the design complexity of System on Chip is increasing very fast. Thus we need huge amount of test pattern to verify the SOC, so how to verify the system effectively is very important. In this thesis, we take the 3DG OpenGL ES2.0 SoC which was developed by our 3DG design group as example, introducing how to build a verification platform with unified method through each level from System Modeling Level to FPGA Emulation Level. Furthermore, we use the automatic verification mechanism to improve the effectiveness of the test pattern and correctness of comparison results. And in order to improve the performance of 3DG OpenGL ES2.0 SoC, we change the original adopted AHB system bus into high performance AXI system bus. We use coreConsultant (developed by Synopsys) to generate the related IP modules, so we can save development and verification time of modules under AXI environment, and we will also introduce the flow of IP generation and synthesis in this thesis.
目次 Table of Contents
Chapter 1. 3D Graphics OpenGL ES 2.0 SoC 1
1.1 3DG OpenGL ES 2.0 SoC Overview 1
1.2 3DG OpenGL ES 2.0 SoC Architecture 2
1.3 3DG OpenGL ES 2.0 SoC Interrupt Mechanism 6
1.4 3DG OpenGL ES 2.0 Processing Flow 7
Chapter 2. Construction and Verification of AXI interconnection 14
2.1 AMBA 3.0 AXI Overview 14
2.2 Feature Comparison of AXI and AHB 17
2.3 Construct the AXI Interconnection Environment 18
2.4 AXI-AHB Bridge 19
2.5 Generic Interface (GIF) Introduction 21
2.6 Verification of IP’s GIF Interface 28
2.7 Verification of IP’s Transaction Combination on 3DG OpenGL ES2.0 SoC 32
2.8 AXI Module Generate, Synthesis and Debugging 35
2.8.1 Module Generation 35
2.8.2 Synthesis Method 39
2.8.3 FPGA Debugging Method 46
Chapter 3. 3DG OpenGL ES2.0 SoC Verification Methodology 52
3.1 System Modeling Level 53
3.2 Register Transfer Level 56
3.3 FPGA Emulation Level 60
3.4 3DG OpenGL ES2.0 SoC Test Patterns 66
3.5 Automatic Verification Mechanism 74
3.6 3DG OpenGL ES 2.0 Verification Coverage 77
Chapter 4. Analysis of 3DG OpenGL ES 2.0 SoC with AXI Interconnection 83
4.1 Synthesis Results of 3DG OpenGL ES2.0 SoC with AXI Interconnection 83
4.2 Performance between 3DG OpenGL ES2.0 with AHB Interconnection and AXI Interconnection 85
4.2.1 Compare Transaction Performance between AHB and AXI Environment 85
4.2.2 3DG OpenGL ES2.0 SoC Test Patterns Simulation Summary 88
4.3 3DG OpenGL ES2.0 Performance Analysis and Improvement Plan 90
Chapter 5. SoC Design for Testing (DFT) 96
Chapter 6. Conclusion 104
Chapter 7. Future Work 105
References 106
Appendix A. 107
Appendix B. 117
Appendix C. 120
參考文獻 References
[1] AMBA 3.0 AXI Specification ARM IHI 0022B
[2] AMBA 2.0 AHB Specification ARM IHI 0011A
[3] ARM, Example AMBA SYstem User Guide ARM DUI0092C
[4] coreConsultant User Guide April 2010
[5] Synopsys FPGA Synthesis User Guide March 2011
[6] Identify User Guide January 2012
[7] VCS MX/VCS MXiTM User Guide Version D-2010.06 June 2010
[8] SystemC-HDL Co-Simulation Manual, Author CoWare, Jul 2007
[9] F. Vahid and T. Givargis, "Embedded System Design".
[10] K. Anjo et al., "Wrapper-Based Bus Implementation Techniques for Performance Improvement and Cost Reduction", Custom LSI Div., NEC Electron. Corp., Kanagawa, Japan; Proceeding Solid-State Circuits, IEEE Journal, May 2004
[11] M. Ebrahimi et al., "Efficient Network Interface Architecture for Network-on-Chips", Dept. of Inf. Technol., Univ. of Turku, Turku, Finland, Proceeding NORCHIP'09, Nov 2009.
[12] 黃威晟 “三維圖形加速系統單晶片之 System/RTL/FPGA/Chip 均一化驗證 方法 A Unified System/RTL/FPGA/Chip Verification Methodology for a 3D Graphics SoC” 國立中山大學碩士論文, 2008.
[13] 黃子銘 “三維圖形加速系統單晶片整合及驗證方法 SoC Integration and Verification of 3D Graphics SoC” 國立中山大學碩士論文, 2011.
[14] B.-G. Nam, et al, ”A Low-Power Vector Processor Using Logarithmic Arithmetic for Handheld 3D Graphics Systems”, ESSCIRC 2007
[15] J.-S. Yoon, et al, ”A 3D Graphics Processor with Fast 4D Vector Inner Product Units and Power Aware Texture Cache”, IEEE CICC 2008
[16] J.-H. Woo, et al, “A 195mW/152mW Mobile Multimedia SoC With Fully Programmable 3-D Graphics and MPEG4/H.264/JPEG”, IEEE JOURNAL of SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SETPTEMBER 2008
[17] David Lin, et al, ” Quick Detection of Difficult Bugs for Effective Post-Silicon Validation”, DAC’12, June 3–7, 2012, San Francisco, CA, USA
[18] Roopak Sinha, et al, “Correct-by-Construction Multi-Component SoC Design”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
[19] Pieter van der Wolf, et al, “SoC Infrastructures for Predictable System Integration”, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011
[20] Vijay D’silva, et al “Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures”, Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE’04)
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