目前主流的數位VLSI設計和邏輯電路合成軟體，皆以互補式金氧半導體(CMOS)邏輯為主，但是在許多應用上，以開關電晶體邏輯（Pass-Transistor Logic, PTL）為主的邏輯電路設計，在面積、速度及功率等方面，均有優異的表現。雖然開關電晶體已經可以達到良好的效能，但目前電路設計自動化軟體工具，在合成電路時考量速度/功率/面積之最佳化時，都是以CMOS電路為主，因此現有的邏輯合成器並無法有效產生PTL電路。本篇論文將提出兩種新的PTL電路合成器設計，其中一種是採用純粹PTL邏輯元件來設計元件電路，另一種則是加入混合PTL/CMOS電路元件來達到在面積、速度及功率等方面更好的結果。開關電晶體電路只須要少數幾種基本電路元件設計和佈局，就能合成所有的電路，因此很適合在製程技術日新月異的奈米時代用來合成單晶片系統（System-on-a-Chip, SoC）。我們所提的PTL邏輯合成器使用Synopsys 設計編譯器 (Design Compiler, DC)，利用標準元件庫的邏輯元件來進行邏輯轉換以及製程對應 (technology mapping)，因此更能有效的嵌入在特殊積體電路標準元件設計流程 (ASIC cell-based design flow)。此篇論文也將探討PTL電路在一些基本的硬體模組設計，以及在算術運算單元及三維繪圖處理器上之應用。

The mainstream of current VLSI design and logic synthesis is based on traditional CMOS logic circuits. However, in the past two decades, various new logic circuit design styles based on pass-transistor logic (PTL) have been proposed. Compared with CMOS circuits, these PTL-based circuits are claimed to have better results in area, speed, and power in some particular applications, such as adder and multiplier designs. Since most current automatic logic synthesis tools (such as Synopsys Design Compiler) are based on conventional CMOS standard cell library, the corresponding logic minimization for CMOS logic cannot be directly employed to generate efficient PTL circuits. In this dissertation, we develop two novel PTL synthesizers that can efficiently generate PTL-based circuits. One is based on pure PTL cells; the other mixes CMOS and PTL cells in the standard cell library to achieve better performance in area, speed, and power. Since PTL-based circuits are constructed by only a few basic PTL cells, the layouts in PTL cells can be easily updated to design large SoC systems as the process technology migrates rapidly in current Nano technology era. The proposed PTL logic synthesis flows employ the popular Synopsys Design Compiler (DC) to perform logic translation and minimization based on the standard cell library composed of PTL and CMOS cells, thus, the PTL design flow can be easily embedded in the standard cell-based ASIC design flow. In this dissertation, we also discuss PTL-based designs of some fundamental hardware components. Furthermore, the proposed PTL cell library is used to synthesize large processor systems in applications of computer arithmetic and 3D graphics.

Acknowledgement i
摘要 ii
Abstract iii
Table of Contents iv
List of Figures vii
List of Tables xi
Chapter 1 Introduction 1
Chapter 2 Survey of Related Works 6
2.1 PTL Circuit Design 6
2.1.1 Previous PTL Circuits 6
2.1.2 PTL vs. CMOS 11
2.2 Pure PTL Synthesis 12
2.3 Hybrid PTL/CMOS Synthesis 14
2.4 Benchmark Circuits 15
Chapter 3 PTL Synthesis with Buffer Elimination 16
3.1 Proposed PTL Synthesis Flow 16
3.1.1 Basic PTL Cells 16
3.1.2 Circuit Design of PINV 17
3.1.3 Overall PTL Synthesis Flow 19
3.2 Technology Mapping Based on PTL Cells 19
3.2.1 One-Level PTL Cells 19
3.2.2 Multi -Level PTL Cells 22
3.3 PTL Logic Simplification 26
3.3.1 Logic Minimization 26
3.3.2 Buffer Elimination 28
3.4 Layout Compaction 31
3.4.1 Separation of Rows for MUX and PINV 33
3.4.2 Merging of Basic PTL Cells 33
3.5 Experimental Results and Comparison 36
3.6 Summary 42
Chapter 4 Hybrid PTL/CMOS Synthesis with Multi-Level PTL Logic 44
4.1 Proposed Hybrid PTL/CMOS Logic Synthesis Flow 44
4.2 Basic PTL Physical Cells 46
4.3 PTL Logic Cells 46
4.3.1 One-Level Logic Cells 46
4.3.2 Multi-Level Logic Cells 48
4.3.3 Some Improvements for PTL Logic Cells 50
4.4 Characterization of PTL Logic Cells 51
4.5 Experimental Results and Comparison 55
4.6 Comparison of Two PTL Synthesis Methods 59
4.7 Summary 63
Chapter 5 PTL Designs for Some Fundamental Circuits 64
5.1 Multiple-Input XOR/XNOR Circuit Design in Cryptography 64
5.1.1 Design of XOR with Multiple Inputs 65
5.1.2 Experimental Results and Comparison 68
5.1.3 Application in AES Design 69
5.2 Design of Full Adder and (4,2) Compressor 71
5.2.1 Full Adder Design 71
5.2.2 Design of (3,2) Counter and (4,2)Compressor Circuits 73
5.3 D Flip-Flop for PTL 79
5.4 Decoder Design 81
5.4.1 Novel PTL Decoder Design 82
5.5 Summary 89
Chapter 6 Applications to the Design of Arithmetic Units and 3D Graphics Processors 90
6.1 Three-Stage ROM/Multiplier-Based CORDIC 90
6.1.1 Original CORDIC Algorithm 90
6.1.2 Multiplier/ROM-Based Implementations 91
6.1.3 Experimental Results and Comparison 98
6.2 Reciprocal Function Evaluation with Hybrid Piecewise Polynomial Approximation and Newton-Raphson Method 100
6.2.1 Hybrid Piecewise Polynomial Approximation and Newton-Raphson Method 100
6.2.2 Unified Architecture 102
6.2.3 Sub-Word-Sharing Architecture 104
6.2.4 Experimental Results and Comparison 107
6.3 3D Graphics Processors 108
6.3.1 Overview of 3D Graphics Pipeline 108
6.3.2 Hardware of Vertex Shader 110
6.3.3 Experimental Results and Comparison 113
6.4 Summary 115
Chapter 7 Conclusions and Future Works 116
7.1 Conclusions 116
7.2 Future Works 116
Bibliography 120

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