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博碩士論文 etd-1027114-003118 詳細資訊
Title page for etd-1027114-003118
論文名稱
Title
整合性系統級封裝中介層測試方法論
An Integrated Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
64
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2014-11-11
繳交日期
Date of Submission
2014-12-04
關鍵字
Keywords
矽穿孔、中介層、二點五維、三維晶片、三維封裝、三維堆疊
3D Stack, 3D Package, 2.5D, 3D IC, Interposer, Through-Silicon Via
統計
Statistics
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中文摘要
本論文提出一組創新的中介層連線(Interposer)的測試架構與方法。數量龐大的
中介層交連線及相對極少數的測試訊號接送及發送端口(Access Ports)使得中介層
交連線難以測試。如仍使用傳統之測試開路錯誤(Open Fault)方法只能達到有限的
錯誤偵測率,因此我們提出一個以測試中介層(Test Interposer)來測試待測試中介
層(Target Interposer)的測試架構,在測試過程中,測試中介層與待測試中介層的
Microbumps 是對位且互相連接的(aligned),以結合這兩塊中介層來提供額外的中
介層交連線,得以將原本未連接的中介層交連線之間建立連線並形成測試路徑
(Test Path),以現場可程式閘陣列(Field Programmable Gate Array, FPGA)注入測試訊
號,使得中介層交連線皆可被測試,實驗結果達到了錯誤偵測率 100%,可以看出
提出的方法的有效性。
我們在[16]提出兩個分別針對開路以及短路錯誤的基礎測試中介層建構法
(BTIC),此論文提出兩個改良[16]測試中介層之建構方法(OTIC, ITIC),第一種為
只針對開路錯誤繞線距離之優化測試中介層建構法(OTIC),第二種為整合優化測
試中介層建構法(ITIC),整合開路與短路錯誤模型,將兩個錯誤模型分別之測試中
介層整合為一個測試中介層,使得測試開路與短路錯誤只需要一個測試中介層,並
進一步優化測試中介層結構產生的演算法以降低繞線成本與針對短路錯誤之常數
級測試時間。
實驗結果顯示,針對開路錯誤,我們提出的優化測試中介層建構法(OTIC)之
繞線成本為 BTIC 的 7%,整合優化測試中介層建構法(ITIC)為 22%,而測試時間
(#TestSession)兩者皆達到常數等級,OTIC 為 1,ITIC 為 4;針對短路錯誤,ITIC
的繞線成本為 BTIC 之 14%,BTIC 的測試時間為 ITIC 的 147 倍。
Abstract
This paper presents a set of novel scheme and corresponding methods for Test
Interposer Interconnects. Testing interposer is difficult due to the large number of
interconnets to be tested and only small number of test access ports available. Previous
methods for PRE-BOND interposer testing can only achieve limited fault coverage for
open faults. We propose to include a test interposer that is aligned with the target
interposer under test in the testing process. Combining these two interposers as a pair will
provide access to interposer nets that are not normally accessible; thus, all interposer
interconnects become testable under our proposed test scheme. The experimental results
show our scheme and methods are effective with all 100% fault testability under both
open and short faults.
We propose one base test interposer construction (BTIC) algorithm for both open
and short faults in [16]. This paper provides two improved BTIC methods. First,
Optimized Test Interposer Construction (OTIC) for open fault; Second, Integrated
Optimized Test Interposer Construction (ITIC). OTIC outperforms BTIC in wirelength
averagely 14.80X for open fault; ITIC integrates two test interposers in BTIC into ONLY
ONE test interposer so we can test open fault and short fault simultaneously with only
one test interposer. Also, ITIC outperform BTIC in wirelength averagely 4.50X for open
fault and 7.08X for short fault. In test time (#TestSession), OTIC, ITIC, and BTIC are
in constant level for open fault, OTIC and BTIC only need 1 TestSession; ITIC needs
four. For short fault, ITIC outperform BTIC 147.75X.
目次 Table of Contents
論文審定書 i
中文摘要 ii
英文摘要 iii
CHAPTER 1 簡介 1
1.1 背景 1
1.2 研究動機 3
1.3 論文架構 4
CHAPTER 2 前提概要 5
2.1 中介層測試架構 5
2.2 測試架構比較 6
CHAPTER 3 測試架構、模型及問題定義 8
3.1 測試架構 8
3.2 測試模型 9
3.3 問題定義 25
CHAPTER 4 測試中介層建構法 28
4.1 測試中介層建構法流程 28
4.2 整合優化測試中介層建構法(ITIC) 29
4.3 優化測試中介層建構法(OTIC) 39
CHAPTER 5 實驗結果 42
5.1 實驗環境與設定 42
5.2 可行性分析 43
5.3 實驗結果 43
5.4 驅動因素分析 45
5.5 演算法分析比較表 47
CHAPTER 6 結論 49
參考文獻 54
參考文獻 References
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