本論文的第一部份提出了使用四個不同相位的三倍電壓產生器。正負極性電壓的產生可用來當做提昇電壓及逆偏壓產生器，所提出的設計是由傳輸電晶體及切換電容所實現。

第二部分提出了低功率離散餘弦轉換。新的離散餘弦轉換及反轉換適合做為可攜性的應用，處理一個8×8區塊的圖素需要花更多的時脈週期，但縮小了晶片的面積，由於減少晶片面積，使得功率消耗下降。

The first topic of this thesis is a novel voltage tripler using 4 clocks with different phases. Both the positive and negative polarities of the voltage are generated to serve as the boosted voltage and the back bias voltage. The proposed design is carried out by pass transistors and switched capacitors.

The second topic is a low-power discrete cosine transform (DCT) processor. It is suitable for portable applications. The number of clock cycles needed for processing an 8×8 block of pixels is increased, but the chip area is reduced. The reduction of the chip area leads to the reduction of the power dissipation.

摘要 i
Abstract ii
第一章 簡介 1
1.1 研究動機 1
1.2 論文目的 2
1.3 論文大綱 3
第二章 應用於記憶體元件的電壓提昇電路 4
2.1 概論 4
2.2 原理架構說明 5
2.2.1 正電壓提昇電路 5
2.2.2 負電壓提昇電路 7
2.2.3 雙極性電壓產生器 9
2.3 晶片模擬結果 10
2.4 效能比較 13
2.4.1 Dickson電壓提昇電路 13
2.4.2 NCP2電壓提昇電路 14
2.4.3本晶片的電壓提昇電路 16
2.4.4 模擬效能的比較 16
2.5 晶片佈局 19
2.6 測試方法及結果 20
2.7 晶片預計規格與實際量測結果 23
2.7.1 晶片預計規格 23
2.7.2 實際量測結果 23
2.8 結論與討論 24
2.9 應用實例 32
2.9.1 在DRAM上的應用 32
2.9.2 在非揮發性記憶體中寫入及消除動作的應用33
第三章 低功率離散餘弦轉換 35
3.1 概論 35
3.2 架構簡介 36
3.3 晶片佈局 40
3.4 晶片的模擬 40
3.5 佈局驗證 42
3.5.1 FPGA驗證 42
3.5.2 TimeMill模擬波形 43
3.6 結論 44
第四章 結論 45
參考文獻 46
附錄 49

[1] A. Bellaouar, and M. I. Elmasry,"Low-power digital VLSI design circuits and systems, ” Reading: Kluwer Academic Publishers, 1995.
[2] I.-Y. Chung, Y. J. Park, and H. S. Min ,“A charge pumping device with a potential barrier using inversion charge transfer, ” IEEE Transactions on Electron Devices, vol. 48, no. 6 , pp. 1216-1221, June 2001.
[3] T. -P. Haraszti, “CMOS memory circuits, ” Reading: Kluwer Academic Publishers, 2000.
[4] S.-W. Kwack, S.-H. Lee, J.-D Joo, B.-G Ko, B.-G. Song, J.-G. Park, and K.-D. Kwack, "A novel substrate-bias generator for low-power and high-speed DRAMs, ” Proceedings of the IEEE Region 10 Conference(TENCON 99), vol. 2, pp.864-867, 1999.
[5] Y. H. Kim, J. K. Nam, Y. S. Sohn, S. C. Heo, S. H. Lee, H. J. Park, Y. S. Han, J. I. Doh, Y. J. Choi,J. H. Choi, and C. S. Park, ”Two-phase boosted voltage generator [CMOS DRAMs],” 6th International Conference on VLSI and CAD (ICVC '99), pp. 586-589, 1999.
[6] H. Lin, and N.-H. Chen, ”An efficient clock scheme for low-voltage four-phase charge pumps,” 2001 Inter. Symp. on VLSI Technology, Systems, and Applications, pp.228-231, 2001.
[7] H. Lin, and N.-H. Chen, ”New four-phase generation circuits for low-voltage charge pumps, ” 2001 Inter. Symp. on Circuits and Systems, vol. 1, pp. 504-507, May 2001.
[8] K.-S. Min and J.-Y. Chung, “A fast pump-down VBB generator for sub- 1.5-V DRAMs, “IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1154-1157, July 2001.
[9] B. Prince, “Semiconductor memories, ”Reading: John Wiley &sons Ltd., 1991.
[10] J.-T. Wu, and K.-L. Chang, ”MOS charge pumps for low-voltage operation, ”IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 592–597,Apr. 1998.
[11] Park, al., “High voltage charge transfer stage, “ Patent 5886566, Mar.1999.
[12] J. F. Dickson, “On-chip high voltage generation in MNOS integrated circuits using an improved voltage multiplier technique, "IEEE J. Solid-State Circuits, vol. 11, no.3, pp.374-378, 1976.
[13] K.-H. Choi, J.-M. PARK, J.-K. Kim, T.-S. Jung, and K.-D. Suh, "Floating-well charge pump circuit for sub-2.0V single power Flash memories,” in Symp. VLSI Circuits Dig. Tech. Papers, pp.61-62, June 1997.
[14] T. Tanzawa, T. Tanaka, “A Dynamic Analysis of the Dickson Charge Pump Circuit”, IEEE J. Solid State Circuits, vol. 32, No. 8, pp. 1231-1240, August 1997.
[15] Ahmed, N.T. Natarajan, and K.R. Rao, "Discrete cosine transform," IEEE Trans. On Computers, vol. C-29, pp. 90-94, Jan.1974.
[16] W. Li, "A new algorithm to compute the DCT and its inverse," IEEE Trans. Signal processing, vol. 39, no. 6, pp. 1305-1313, June 1991.
[17] F. Jutand, N. Demassieux, G. Concordel, J. Guichard, and E. Casimatis, "A single chip video rate 16×16 discrete cosine transform," in proc. IEEE ICASSP’86, pp805-808, Dec. 1986.
[18] Peled, B. Liu, "A new Hardware Realisation of Digital Filters," IEEE Trans. on Acoustics, Speech, and Signal Processing Magazine, vol.22(6), pp. 456-462, Dec. 1974.
[19] W. H. Chen, C. H. Smith, and S. C. Fralick, "A fast computational algorithm for the discrete cosine transform,"IEEE Transactions on Communications, vol.COM-25, no. 9, pp. 1004-1009, Sep. 1977.
[20] T. Masaki, Y. Morimoto, T. Onoye, and I. Shirakawa, "VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV decoding," IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 5, pp.387-395, Oct. 1995.
[21] J. Park, S. Kwon, and K. Roy, “Low power reconfigurable DCT Design based on sharing multiplication,”IEEE Inter. Conf. on Acoustics,
Speech, and Signal Processing , vol. 3, no.3, pp. 3116-3119, May. 2002.
[22] M. Hamada, T. Terazawa, T. Hisash, and S. Mita, “Flip-flop selection technique for power-delay trade-off, ” IEEE Inter. Solid-State Circuit Conf. Sec. 15, pp. 270-271, Feb. 1999.