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博碩士論文 etd-1104102-123211 詳細資訊
Title page for etd-1104102-123211
論文名稱
Title
使用雙門檻電壓之可同步�非同步選擇4-電晶體靜態隨機存取記憶體
Synchronous/Asynchronous 4-T SRAM Using Dual Threshold Voltage
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
74
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2002-10-29
繳交日期
Date of Submission
2002-11-04
關鍵字
Keywords
假警報訊號、工作週期、位址線轉變偵測器
False alarm, Strobe, Address transition detector
統計
Statistics
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The thesis/dissertation has been browsed 5633 times, has been downloaded 0 times.
中文摘要
中文提要:
本論文共涵蓋兩個不同的主題:第一部份為實作一使用低臨界電壓N電晶體為字元線驅動器與高臨界電壓P電晶體為儲存閂鎖之4K位元500 MHz 4-電晶體靜態隨機存取記憶體。我們使用一反相連接P電晶體對來儲存資料,而使用N電晶體對作為位元線控制器。使用雙檻電壓電晶體的好處是可以減少資料存取時間以及維持資料的正確性。

第二部份為實作一串接式抗雜訊之位址線轉變偵測器。我們使用一個簡單的迴授電路來抵抗雜訊和假警報訊號 (False Alarm Signal) 的干擾,並產生一個穏定的晶片選擇訊號 (Chip Select,簡稱為CS)。此外,我們可以藉由調整一個延遲緩衝元件來動態的調整晶片選擇訊號的工作週期 (Strobe)。


Abstract
英文提要:
Two different topics associated with their respective applications are proposed in this thesis. The first topic is focused on the implementation of a 4-Kb 500MHz 4-T CMOS SRAM using low-Vthn bitline drivers and high-Vthp latches. The storage of data is realized by a pair of cross-coupled PMOS transistors, while the wordline is controlled by a pair of NMOS transistors. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time.

The second topic is the implementation of cascade address transition detector (ATD) design with high noise immunity. We employ a feedback loop to prevent interference of noise and false alarm signal to stabilize the generated CS (Chip Select) signal. Besides, we use one delay buffer to dynamically adjust the CS strobe.


目次 Table of Contents
摘要 I
ABSTRACT II
圖目錄 VI
表目錄 IX
第一章 簡介 1
1.1研究動機與目的 1
1.2先前相關文獻討論 2
1.3論文目的 4
1.4論文大綱 4
第二章 可同步/非同步選擇4-電晶體靜態隨機存取記憶體 6
2.1概論 6
2.2架構簡介 10
2.2.1 行架構 (column structure) 11
2.2.2 記憶單元 (SRAM cell) 之架構和效能說明 12
2.2.3 預放電電路 (predischarge circuit) 之優點 19
2.2.4 內建自我測試 (BIST) 電路 20
2.2.5 其他模組電路 22
2.3 模擬結果 23
2.3.1 同步操作模式之模擬結果 23
2.3.2 非同步操作模式之模擬結果 25
2.3.3 內建自我測試模式模擬結果 26
2.3.4 操作規格 27
2.4 測試結果與晶片佈局 28
2.4.1測試方法及結果 28
2.4.2 晶片佈局 36
2.5結論 38
已發表之論文名稱 39
第三章 串接式抗雜訊之位址線轉變偵測器 40
3.1概論 40
3.2設計方法與電路架構 41
3.2.1第一級位址偵測電路 41
3.2.2第二級位址偵測電路 42
3.2.3 ATD電路的整合方法 43
3.3晶片模擬結果 45
3.3.1第二級位址偵測電路之模擬結果 45
3.3.2串接式位址線轉變偵測電路的模擬結果 46
3.4測實結果與晶片佈局 49
3.4.1測試方法與測試結果 49
3.4.2晶片佈局與照相圖 55
3.5結論 57
第四章 總結 58
參考文獻 60

參考文獻 References
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[10] B. Wicht, S. Paul, and D. Schmitt-Landsiedel, “Analysis and compensation of the bitline multiplexer in SRAM current sense amplifiers,” IEEE J. Solid-State Circuits, vol. 36, no. 11, pp. 1745-1755, Nov. 2001.

[11] K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, “A bit-line leakage compensation scheme for low-voltage SRAM's,” 2000 Symposium on VLSI Circuits Digest of Technical Papers, pp. 70-71, 2000.
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[14] C.-C. Wang, P.-M. Lee, and K.-L. Chen, “6-T SRAM using dual threshold voltage transistors and low-power quenchers,” 9th IEEE International Conference on Electronics, Circuits and Systems (ICECS’2002), (no. 1115, Apr. 2002, accepted).

[15] F. Miyaji, Y. Matsuyama, Y. Kanaishi, K. Senoh, T. Emori, and Y. Hagiwara, “A 25 ns 4 Mb CMOS SRAM with dynamic bit line loads,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1213-1218, Oct. 1989.

[16] 陳國龍,“使用具有低功率止擾器雙門檻電壓之6-電晶體靜態記憶體與可程式化鎖相迴路式倍頻之晶片設計與實作”,中山大學電機工程學系碩士論文,民國九十一年六月。

[17] 王俊傑,“使用表格分享設計混合式高基底64b/32b整數除法器設計與實作”,中山大學電機工程學系碩士論文,民國九十年六月。

[18] C.-C. Wang, and J.-J. Wang, ``Address transition detector with high noise immunity,' 2001 The 12th VLSI Design/CAD Symposium, C3-3, pp. 62, Aug. 2001.

[19] K. Noda, K. Matsui, K. Takeda, and N. Nakamura, “A loadless CMOS four-transistor SRAM cell in a 0.18-/spl mu/m logic technology Electron Devices,” IEEE Transactions, vol. 48, no. 12, pp. 1745-1755, Dec. 2001.

[20] K. Agawa, H. Hara, T. Takayanagi, and T. Kuroda, “A bitline leakage compensation scheme for low-voltage SRAMs,” IEEE J. Solid-State Circuits, vol. 36, no. 5, pp. 726-734, May 2001.

[21] K. Noda, K. Takeda, K. Matsui, S. Masuoka, H. Kawamoto, N. Ikezawa, Y. Aimoto, N. Nakamura, T. Iwasaki, H. Toyoshima, and T. Horiuchi, “An ultrahigh-density high-speed loadless four-transistor SRAM macro with twisted bitline architecture and triple-well shield,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 510-515, March 2001.

[22] C.-C. Wang, H.-Y. Leo, and R. Hu, “A 4-Kb 500-MHz 4-T CMOS SRAM using low-VTHN bitline drivers and high-VTHP latches,” 2002 IEEE ASIA-Pacific Conference on ASICs, pp. 49-52, Aug. 2002.
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