本論文提出了一個整合開發環境，並且提供圖形化介面產生以及評估容錯相關技術之處理器，使用者可以透過圖形化介面選擇硬體容錯(雙核心同步檢查微處理器亦或是針對記憶體的錯誤檢查碼和錯誤更正碼)，當使用者選取選項後，此平台可產生出相對應的配置檔案；此外，應用程式也可經由分析器產生具有可偵測程式執行流程正確性之程式碼。這個工作平台亦與硬體模擬器結合，提供錯誤注入的功能，對於使用者所選取的容錯配置，初步給予錯誤偵測能力的評估。我們將這些功能與晶心科技N801s之微處理器做結合，對於不同的配置，圖形化介面提供效能評估、成本分析、錯誤覆蓋率等資訊供使用者參考，如此一來，便可針對不同的應用以及需求產生相對應的軟硬體以達到最高的價值。

We present an integrated development environment (IDE) with GUI for generating and evaluating the fault-tolerant microprocessor. Designer can select from hardware options (dual-core for microprocessor, error detection code or error correction code for memory) and automatically generates configuration file for RTL code. In addition, the application can be encoded by our Analyzer and generate signature augmented program to detect the control-flow error in the run-time. In the end, it also performs simulation-based fault injection campaign to evaluate the fault detection capabilities of different fault-tolerant configurations. The IDE and GUI have been implemented for Andes N801s microprocessor core. This workbench would also provide estimated performance, cost overheads and fault coverage for the generated fault-tolerant architecture in order to suite different safety level applications or user requirements.

論文審定書 i
中文摘要 iii
Abstract iv
List of Figures vii
List of Tables ix
Chapter 1. Introduction 1
1.1 Background 1
1.2 Motivation 2
1.3 Organization of the Thesis 3
Chapter 2. Related Works 4
2.1 Software-Based Fault-Tolerant Approaches 4
2.2 Hardware-Based Fault-Tolerant Approaches 7
2.2.1. Symmetric and Asymmetric Architecture 7
2.2.2. EDC and ECC code 8
2.3 Fault Injection 10
2.3.1. Physical Fault Injection 10
2.3.2. Software-Based Fault Injection 10
2.3.3. Simulation-Based Fault Injection 11
Chapter 3. Introduction of Workbench 13
Chapter 4. Software-Based Approach 17
4.1 Criteria for Selecting Software Approaches 18
4.2 Introduction of CEDA algorithm 23
4.3 Implementation in the Software-Based Approach 26
4.3.1. Implementation Level 26
4.3.2. Performance Issue 27
4.3.3. The Flow of Signature Insertion 28
Chapter 5. Hardware-Based Approaches 33
5.1 SED and SEC 34
5.2 Symmetric Architecture 34
Chapter 6. Simulation-Based Fault Injection 36
Chapter 7. How to Reuse Workbench 39
7.1 Reuse Software Fault-Tolerant Method 39
7.2 Reuse Hardware Fault-Tolerant Methods 45
7.3 Reuse Simulation-Based Fault Injection 47
Chapter 8. Case Study 49
8.1 Set Up for Experiment 49
8.2 Experiment Result 51
Chapter 9. Conclusion and Future Work 53
Bibliography 54
Appendix A. Introduction of N801-S processor 58

[1] AndesCore™ N801-SData Sheet, Andes Technology Corporation
[2] GCC, the GNU Compiler Collection
[3] AsicGuru.com - Introduction to SystemVerilog
[4] M.A. Schuette and J.P. Shen, “Processor Control Flow Monitoring Using Signatured Instruction Streams,” IEEE Trans. Computers, vol. 36, no. 3, pp. 264-276, Mar. 1987.
[5] Gunneflo, U., Karlsson, J., Torin, J., “Evaluation of error detection schemes using fault injection by heavy-ion radiation,” International Symposium on Fault-Tolerant Computing, 1989., pp. 340-347
[6] J. Ohlsson, M. Rimen, and U. Gunneflo, “A Study of the Effects of Transient Fault Injection into a 32-Bit Risc with Built-In Watchdog,” Proc. 22nd Int’l Symp. Fault Tolerant Computing, pp. 316-325, 1992.
[7] Jenn, E., Arlat, J., Rimen, M., Ohlsson, J., Karlsson, J., “Fault injection into VHDL models: the MEFISTO tool,” International Symposium on Fault-Tolerant Computing, 1994., pp. 66-75
[8] N. Krishnamurthy, V. Jhaveri, and J.A. Abraham, “A Design Methodology for Software Fault Injection in Embedded Systems,” Proc. IFIP Int’l Workshop Dependable Computing and Its Applications (DCIA ’98), pp. 237-248, Jan. 1998.
[9] Alkhalifa, Z., Nair, V.S.S., Krishnamurthy, N., Abraham, J.A., “Design and evaluation of system-level checks for on-line control flow error detection,” IEEE Transactions on Parallel and Distributed Systems, Jun 1999, pp. 627-641
[10] Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B., “MiBench: A free, commercially representative embedded benchmark suite,” 2001 IEEE International Workshop on Workload Characterization.
[11] Oh, N. ; Shirvani, P.P. ; McCluskey, E.J, “Control-flow checking by software signatures”, IEEE Transactions on Reliability, 2002
[12] Goloubeva, O., Rebaudengo, M., Reorda, M.S., Violante, M., “Soft-error detection using control flow assertions,” 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2003, p.p. 581-588
[13] Venkatasubramanian, R., Hayes, J.P., Murray, B.T., “Low-Cost On-Line Fault Detection Using Control Flow Assertions”, 9th IEEE On-Line Testing Symposium, p.p. 137-143
[14] R. Mariani, P. Fuhrmann, B. Vittorelli, “Cost-effective Approach to Error Detection for an Embedded Automotive Platform”, 2006-01-0837, SAE 2006 World Congress & Exhibition, April 2006, Detroit, MI, USA
[15] Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter , “Recovery Mechanisms for Dual Core Architectures”, International Symposium on Defect and Fault Tolerance in VLSI Systems, 2006
[16] Meixner, A., Duke Univ., Durham, Sorin, D.J., “Error Detection Using Dynamic Dataflow Verification”, 16th International Conference on Parallel Architecture and Compilation Techniques, 2007.
[17] Shokrolah-Shirazi, M., Miremadi, S.G., “FPGA-Based Fault Injection into Synthesizable Verilog HDL Models,” Second International Conference on Secure System Integration and Reliability Improvement, 2008, p.p. 143-149
[18] Bianca Schroeder, Eduardo Pinheiro, Wolf-Dietrich Weber, “DRAM errors in the wild: a large-scale field study,” Proceedings of the Eleventh International Joint Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2009, pp. 193–204. ACM, New York, USA
[19] David Kammler, Junqing Guan, GerdAscheid, Rainer Leupers, Heinrich Meyr, ”A Fast and Flexible Platform for Fault Injection and Evaluation in Verilog-Based Simulations”,2009 Third IEEE International Conference on Secure Software Integration and Reliability Improvement
[20] Aiguo Li, Bingrong Hong, “On-line control flow error detection using relationship signatures among basic blocks,” Journal, Computers and Electrical Engineering archive, January, 2010, p.p 132-141
[21] Lei Xiong, Qingping Tan, “Data Flow Error Recovery with Checkpointing and Instruction-Level Fault Tolerance”, 12th International Conference on Parallel and Distributed Computing, Applications and Technologies (PDCAT), 2011.
[22] Vemu, R. ; Intel Corp., Chandler, AZ, USA ; Abraham, J.A. ; “CEDA: Control-Flow Error Detection Using Assertions,” IEEE Transactions on Computers, 2011., pp. 1233-1245
[23] AbdurRouf, M. ,Soontae Kim, “Low-cost Control Flow Error Protection by Exploiting Available Redundancies in the Pipeline”, Design Automation Conference (ASP-DAC), 2012 17th Asia and South Pacific
[24] Shirazi, M.S., Morris, B, Selvaraj, H., “Fast FPGA-based fault injection tool for embedded processors,” International Symposium on Quality Electronic Design, 2013., pp. 476-480
[25] Chaudhari, A., Junyoung Park, Abraham, J., “A Framework for Low Overhead Hardware Based Runtime Control Flow Error Detection and Recovery,” 2013 IEEE VLSI Test Symposium (VTS)
[26] Asghari, S.A., Taheri, H., Pedram, H., Kaynak, O., “Software-Based Control Flow Checking Against Transient Faults in Industrial Environments,” IEEE Transactions on Industrial Informatics, 2013, p.p. 481-490
[27] Pournaghdali, F., Rajabzadeh, A., Ahmadi, M., “VHDLSFI: A simulation-based multi-bit fault injection for dependability analysis,” International Conference on Computer and Knowledge Engineering (ICCKE), 2013., pp.354-360
[28] Ping-Chun Lee, Ing-Jer Huang, “Reconfigurable Bus Monitor Tool Suite for on-chip SoC for performance and protocol monitoring,” 2014 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip