因SRAM在如智慧型手機等之可攜式消費性電子產品中的功率消耗佔有相當高之比率，因此減少功率消耗為SRAM設計中一重要技術。因此，在本論文中提出兩種針對5T SRAM單元所設計之補償電路。

第一個電路設計為SRAM輸出訊號之迴轉率補償電路，當中包含一漏電流偵測電路及一電流補償電路。當電路操作於漏電流過大之狀況時，漏電流偵測電路將輸出一始能訊號以啟動電流補償電路，而電流補償電路將提供一額外電流增加SRAM單元之輸出訊號迴轉率。而迴轉率的提升可加速後端數位電路儘早操作於穩定狀態，如此一來整體電路的功率消耗也可隨之降低。此設計係以TSMC 40 nm CMOS元件庫技術進行佈局及下線，根據晶片量測結果得知在系統電壓為0.6 V時，只需付出3.64% 之面積即可減少27.86% 之功率及54.88%之讀取延遲。

第二個設計為一閘極電壓提升補償電路，當中包含一電壓調適電路及一電壓提升電路。在操作於高壓時(漏電流較高)，藉由提升存取電晶體之閘極電壓以提升讀寫電流，進一步提升整體SRAM之操作頻率。此設計係以TSMC 28 nm CMOS低功率元件庫技術進行佈局及下線，根據晶片量測結果證實系統電壓為0.8 V時，付出6.6%的面積即可減少17.2%的功率消耗及提升46.5%之迴轉率。

上述之新提出之設計，使本論文之SRAM在綜合效能指標(FOM)表現上，達到目前為世界領先者。

To reduce the SRAM area, a 5T single-ended SRAM cell has been proposed by our laboratory before. This dissertation presents two compensation designs for the 5T single-ended SRAM to reduce the power consumption of consumer electronics, e.g., smartphones.

The first compensation design is a Slew Rate Compensation Circuit to fasten the slew rate of output signals. This compensation circuit consists of a Leakage Current Sensor and a Current Compensation Circuit. When the leakage of the SRAM cell is too high, the Current Compensation Circuit will be enabled by the Leakage Current Sensor to elevate the slew rate of the output on the bitline. This makes it possible to speed up the subsequent digital circuitry into a stable state, thereby reducing the associative active power.The SRAM using the proposed design was implemented using TSMC 40 nm CMOS logic technology. At the system voltage of 0.6 V, the proposed compensation design reduced the average power dissipation by 27.86%, and read delay by 54.88%, with only 3.64% area overhead.


The second compensation design is to add a circuit in the SRAM cell to boost the gate voltage of the access transistor, thereby allowing an increase in the slew rate of the output, resulting in faster read and write operations. The SRAM using this gate drive boost circuit was implemented using TSMC 28 nm CMOS logic low power technology. When operating at a system voltage of 0.8 V, the proposed compensation scheme was demonstrated to reduce power dissipation by 17.2% and attain a 46.5% improvement in the output slew rate with only 6.6% area overhead.

Finally, two compensation circuits are implemented using 40 nm and 28 nm logic processes to justify their performance, respectively. According to the Figure-of-Merit (FOM), the SRAMs using the proposed compensation designs have been proved are the state of art to date of the 5T single-ended SRAMs.

中文摘要i
Abstract ii
List of Figures vi
List of Tables ix
Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 SRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Compensation Schemes . . . . . . . . . . . . . . . . . . . . . . 9
1.3 Organization of the Dissertation . . . . . . . . . . . . . . . . . . . . . 15
Chapter 2 5T SRAM with Slew Rate Compensation 17
2.1 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2 Single-ended Disturb-free 5T Loadless SRAM Cell . . . . . . . . . . . 18
2.2.1 Read and Write Access . . . . . . . . . . . . . . . . . . . . . . 19
2.2.2 Optimal number of cells to share one bitline inverter . . . . . 21
2.3 Slew Rate Compensation Circuit . . . . . . . . . . . . . . . . . . . . 24
2.3.1 Leakage Current Sensor . . . . . . . . . . . . . . . . . . . . . 24
2.3.2 Current Compensation Circuit . . . . . . . . . . . . . . . . . . 27
2.4 Row/Column decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
2.5 Build-in Self-test (BIST) . . . . . . . . . . . . . . . . . . . . . . . . . 31
iv
2.6 Implementation and Measurement . . . . . . . . . . . . . . . . . . . . 32
2.6.1 Simulation results . . . . . . . . . . . . . . . . . . . . . . . . . 32
2.6.2 Chip measurement . . . . . . . . . . . . . . . . . . . . . . . . 37
2.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Chapter 3 5T SRAM with Gate Drive Boosting Compensation
Circuit 47
3.1 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.2 Single-ended Disturb-free 5T Loadless SRAM Cell . . . . . . . . . . . 48
3.3 Gate Drive Boosting Compensation Circuit . . . . . . . . . . . . . . . 49
3.3.1 Adaptive Voltage Detector (AVD) . . . . . . . . . . . . . . . . 50
3.3.2 Word Line Boost Circuit (WLBC) . . . . . . . . . . . . . . . . 52
3.4 Implementation and Measurement . . . . . . . . . . . . . . . . . . . . 55
3.4.1 Simulation and analysis . . . . . . . . . . . . . . . . . . . . . 55
3.4.2 Chip measurement . . . . . . . . . . . . . . . . . . . . . . . . 60
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Chapter 4 Conclusion and Future Work 68
4.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
4.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Bibliography 73

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