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博碩士論文 etd-1121117-102836 詳細資訊
Title page for etd-1121117-102836
論文名稱
Title
心電訊號感測系統之類比前端電路與時頻分析設計
Analog Front-end Circuits and Time-Frequency Analysis Design for ECG Sensing System
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
116
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-12-20
繳交日期
Date of Submission
2017-12-21
關鍵字
Keywords
滑動式離散型傅利葉轉換、儀表放大器、前端類比讀取
front-end circuit, sliding discrete Fourier transform, Instrumentation amplifier
統計
Statistics
本論文已被瀏覽 5653 次,被下載 6
The thesis/dissertation has been browsed 5653 times, has been downloaded 6 times.
中文摘要
近年來無線電子醫療系統需求性日益增加,開發出利用穿戴式感測器並結合可攜式資料分析裝置,且在不影響日常生活作息之下,用來監測患者的生理參數之新穎式醫療照護系統顯得格外重要。基於此概念,本論文設計出一搭載自製晶片之心電訊號讀取與分析監測平台,其平台主要可分為三大區塊,分別為:(1)由儀表放大器、帶通濾波器、增益電路和類比數位轉換器所組成的前端類比讀取電路;(2) 用於處理Hanning window摺積運算之數位訊號處理器;(3)由滑動式離散型傅利葉轉換所組成的後端分析電路。
在平台實際操作上,首先透過前端讀取電路將量測之心電訊號轉換成數位碼,緊接著由處理器將心電資料進行Hanning window之訊號前處理,最後在由後端分析電路進行頻譜轉換處理,實現心電訊號之時間-頻率分析之應用。
在前端讀取電路以及後端分析電路之晶片實現上,我們採用TSMC CMOS 0.18µm製程。首先前端讀取晶片內部包含一具有89dB共模拒斥比以及88dB電源拒斥比特性之儀表放大器、Multiple Feedback帶通濾波器、增益模組與連續漸進暫存式類比數位轉換器,而轉換器取樣頻率為1-KHz條件之下,可以量測出SNDR為58.8dB,有效位元(ENOB)為9.4bit,實際晶片面積為1.599 X 1.146mm2,總動態功率消耗為0.238mW。其次為後端分析處理晶片,由電路合成結果可知Gate Count數為73,446個,實際晶片面積為1.151 X 1.141 mm2,工作频率為1-KHz條件之下總動態功率消耗為1.62μW。時頻分析處理器與現有文獻比較,乘法運算量節省80.35%與加法運算量節省54.91%,有效降低系統複雜度與面積等問題。本次設計的晶片上,具有小面積與低功耗等特點,將可以協助我們開發出一輕便、節能之生醫檢測裝置設計。
Abstract
Recently, the demand for wireless electronic medical devices has been greatly increased. The innovation of wearable sensors with a portable data analysis device can not only monitors medical parameters of the patient under the less affection to human’s daily activities. Based on above design target, we design several chips for the implementation of the measuring and analyzing platform which includes the following three parts: (1) A front-end readout circuit is composed of Instrumentation Amplifier (IA), band-pass filter, gain stage, and Analog-to-Digital Converter (ADC); (2) A digital signal processor on Field-Programmable Gate Array (FPGA) is responsible for handling the convolution operation of Hanning window; (3) A back-end analysis circuit is composed of sliding discrete Fourier transform (SDFT);
The operational steps for the proposed platform are as follow: (1) we convert electrocardiogram (ECG) signals to digital codes through the front-end circuit; (2) the processor on FPGA will deal with the ECG digital codes by multiplying the cefficients of Hanning window; (3) the time-domain ECG digital codes are converted into the spectrum results through the SDFT circuit, and then the time-frequency analysis is achieved.
The proposed design is realized by using TSMC CMOS 0.18-µm technology. The proposed IA has 89dB CMRR and 88dB PSRR. Under a 1-kHz sampling rate, the SNDR and ENOB of the proposed SAR ADC are 58.8dB and 9.4bit. The chip area and total power consumption of analog circuit chip area are 1.599X1.146mm2, and 0.238mW, respectively. Under a 1-kHz operating frequency, the gate count, chip area, and power consumption of the proposed time-frequency processor are 73446, 1.151X1.141mm2, and 1.62μW, respectively. The time-frequency module compared with Krzysztof Duda’s method, the number of multiplication and addition are achieve 80.35% and 54.91% reducing, respectively. Therefore, the proposed platform can achieve low-complexity and area effectively. We believe it can help us to develop a portable and low-power detecting device in the future.
目次 Table of Contents
論文審定書 i
誌謝 ii
中文摘要 iii
ABSTRACT iv
目錄 vi
圖目錄 viii
表目錄 xi
第一章 緒論 1
1.1 研究目的與動機 1
1.2 論文章節組織 4
第二章 研究背景與文獻回顧 5
2.1 研究背景 5
2.2 文獻回顧 13
第三章 生醫感測系統 16
3.1 前端讀取電路設計 16
3.1.1 儀表放大器 17
3.1.2 帶通濾波器電路設計(Bandpass Filter) 19
3.1.3 增益電路設計(Gain-Stage) 25
3.2 連續漸近暫存式類比數位轉換器 27
3.2.1 電路理論與運作原理 27
3.2.2 非理想效應 30
3.2.3 電路設計 30
3.2.3.1 追蹤保持電路(Tack and Hold, T/H) 30
3.2.3.2 比較器(Comparator) 33
3.2.3.3 數位類比轉換器 36
3.2.3.4 SAR控制電路 38
3.3 時頻分析處理器設計 39
3.3.1 新型滑動式離散傅利葉轉換推導 41
3.3.2 演算法核心處理單元設計 48
3.3.3 硬體架構設計 50
3.3.4 降低ROM係數方法 51
3.3.5 記憶單元的控制 53
3.3.5.1 RAM控制電路設計 53
3.3.5.2 ROM控制電路設計 54
第四章 系統電路模擬結果 55
4.1 類比前端電路模擬 55
4.1.1 儀表放大器模擬 55
4.1.2 運算放大器模擬 65
4.1.3 SAR ADC模擬 73
4.1.4 前端晶片佈局 76
4.2 時頻分析處理器電路模擬 78
4.2.1 時頻分析處理器晶片佈局 80
第五章 量測方法與結果 82
5.1 DDA量測與結果 82
5.2 OPA量測與結果 87
5.3 SAR ADC量測與結果 90
5.4 Sliding DFT整合量測與結果 93
第六章 總結與未來展望 97
參考文獻 99
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