Responsive image
博碩士論文 etd-1130115-111134 詳細資訊
Title page for etd-1130115-111134
論文名稱
Title
奈米線電晶體在矽覆絕緣之分析與模型
Analysis and Modeling of Nanowire MOSFETs on SOI Substrate
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
182
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-12-29
繳交日期
Date of Submission
2016-01-06
關鍵字
Keywords
製作技術、離散摻雜影響、三維數值模擬、鰭式場效應電晶體、無接式場效應電晶體、鍺與III-V整合、精簡模型、奈米線、設計窗
Junctionless, Compact Model, Bulk FinFET, semiconductor technology technique for manufacturing, TCAD Simulation, Random Dopant Fluctuation, III-V and Ge, Nanowire, Design Window
統計
Statistics
本論文已被瀏覽 5766 次,被下載 71
The thesis/dissertation has been browsed 5766 times, has been downloaded 71 times.
中文摘要
場效應電晶體從1947年被發明至今,走過無數的蛻變,從單純的尺寸微縮,由光學步進曝光機到電子束微影系統微縮至20奈米。從高K值氧化層選擇與金屬閘極選擇,汲源極矽鍺應力增強。氧化層上矽的使用,衝擊離子化特性使邏輯運算速度增快,然而,場效應電晶體即將走入多閘極鰭式電晶體量產,傳統場效應電晶體與多閘極之間是否存在共通的設計?是本論文所研究的主軸。
本論文主要從場效應電晶體的設計窗之研究,考量各種參數對於奈米線電晶體的影響,從傳統場效應電晶體的設計窗為出發點,延伸至與最具微縮性的奈米線場效應電體研究,透過學理分析與三維數值模擬,深入探討奈米線電晶體微縮能力,以及對抗短通道效應的能力。此外,我們也對於環繞式閘極的電容特性,做一精簡模型,與傳統的平面式計算的差別,最後與TCAD相互驗證。
而製程技術不斷的持續進步,在極度微縮的過程中,摻雜在電晶體中的難度也隨著急速上升,在傳統電晶體中離散摻雜影響十分嚴重,本文也對於離散摻雜效應在多閘極電晶體下特性比較,根據傳統的設計,使其離散分佈在通道中,使用統計方式比較其特性走向;而無接式場效應電晶體的發明,使摻雜困難度減低,也是本文討論的目標。離散原子是否也如傳統電晶體設計般,有嚴重的臨界電壓差異?或者有其他主要影響臨界電壓的因子存在?本論文採用高斯分佈來設計離散原子在無接面式電晶體中的影響,並同時討論氧化層厚度、矽薄膜厚度、金屬工函數影響與閘極致汲源延伸區,歸納出製程上影響臨界電壓最劇烈的參數。
而在製作技術上,鰭式場效應電晶體的製作已成為主流,在製程中可以微縮與應用的參數,本論文也將其討論相關製作方式,最後與先前的推論做驗證。然而,如何超越摩爾定律?在本論文中也提供兩種設計方式,其中一種是衝擊離子化在多閘極場效應電晶體,以具有微縮代表性的奈米線為範例,其次為非矽半導體整合,以鍺與III-V整合在同一基板為出發,延伸鰭式場效應電晶體的技術,在主要不同的主動區為探討製作上的差異。
Abstract
The MOSFET transistor devices have been invented since 1947. From I-Line dimension to E-beam writer, MOSFETs have gone through a series of revolution in semiconductor industry such as high-k dielectrics oxide and metal gate. The source/drain material is now implemented with SiGe for strain purpose. SOI technology has been used in logic design, unique impact ionization of which can be beneficial to performance. Among multiple-gate devices, FinFET is emerging for manufacturing. How to account for the new physics of multiple gate devices in logic design is addressed in this thesis. Furthermore, the thesis also presents some issues and solutions when applying for the conventional design window to the multiple gate devices.
This thesis reviews the design window of MOSFET devices based on conventional bulk transistors, which can be extended to nanowire transistor design. A comprehensive yet simple design methodology of silicon nanowire MOSFETs is presented. An analytical gate capacitance model for sub-22 nm gate length is also proposed to gain insight into design optimization with quantum confinement included. In contrast to conventional bulk device design, this thesis shows that the wire diameter does not necessarily follow the common stringent scaling rule. An optimal device design window does exist while a moderate wire diameter dimension is suggested without the need of extremely scaled dimension.
When the devices technology continues to scale, the doping engineering is becoming more difficult. This thesis presents a detailed analysis on the variation sources in junctionless double-gate transistors using numerical device simulation. Comparison with conventional ultra-scaled devices is also included in the study. When channel thickness is reduced to 10 nm or below, thickness variation becomes the predominant source of threshold voltage variation even though random dopant fluctuation has been considered the most significant one, especially in the highly doped junctionless channel. When accounting for volume inversion in the thin silicon film, we propose a modeling approach to estimate the film thickness variation impact on threshold voltage using effective film thickness. Our study suggests that when the ratio of film thickness to channel length is less than one quarter, the threshold voltage becomes less sensitive to film thickness variation, partly due to quantum confinement.
As end of technology roadmap is being approached, many solutions to extend Moore’s Law have been proposed. When the device dimension continues to shrink, and the leakage current, mainly coming from the short-channel effects, becomes a limiting factor, the supply bias, i.e. VDD, has to decrease accordingly. However, in order to provide a good CMOS logic function, the transistor on-off current ratio, which is linked to subthreshold swing, has to stay above at least four orders. Such limitation has prevented the supply bias from further reduction. For low power application, the off leakage current is strictly limited. To gain better performance at same leakage, we will need to lower swing. The subthreshold kink effect enables the use of low supply bias without compromising performance for gate-all-around MOSFETs. This thesis is organized as follows; Chapter 1 introduces the semiconductor technology technique for manufacturing bulk FinFETs. Chapter 2 presents nanowire device scaling and design window. Chapter 3 presents a study of junctionless MOSFETs with a focus on random doping fluctuation effect. Chapter 4 presents beyond Moore’s law including the super steep subthreshold swing design and Chapter 5 presents future work on the silicon integration of Ge and III-V.
目次 Table of Contents
摘要 i
Abstract iii
CONTENTS vi
Figure Caption ix
Table Caption xix
Chapter 1 Introduction 1
1 - 1. MOSFET Evolution 1
1 - 2. Device scaling and Motivation 3
1 - 3. Bulk FinFET Manufacture and calibration 4
1 - 4. Bulk FinFET Experiment Results and Discussion 13
1 - 5. Summary 24
Chapter 2 Nano Device Scaling and Design Window 25
2 - 1. Design Introduction 26
2 - 2. Scaling insight and performance projection 28
2 - 3. Analysis for design considerations 37
2 - 3 - 1. Design consideration for bulk mosfets 37
2 - 3 - 2. Design consideration for nanowire mosfets 39
2 - 4. Evaluation of nanowire diameter 42
2 - 5. Summary 47
Chapter 3 Random Doping Fluctuation and Junctionless Study 48
3 - 1. Simulation Techniques for Nanowire Transistors 50
3 - 1 - 1. Results and Discussion 52
3 - 1 - 2. Discrete Dopant Fluctuation along the Channel 54
3 - 1 - 3. Discrete Dopant Fluctuation across the Wire 56
3 - 1 - 4. Variability in Silicon Nanowire MOSFETs 59
3 - 1 - 5. Summary 60
3 - 2. Junctionless Nanowire FET on SOI Substrate 61
3 - 2 - 1. Design Introduction 61
3 - 2 - 2. Simulation methodology 62
3 - 2 - 3. Performance Comparison 64
3 - 2 - 4. Summary 72
3 - 3. Threshold Voltage Variability Analysis and Design Insights for Junctionless Double-Gate Transistors 73
3 - 3 - 1. Design Introduction 73
3 - 3 - 2. Random Discrete Doping for Double- Gate Transistors 75
3 - 3 - 3. Comprehensive analysis to account for additional fluctuations 78
3 - 3 - 4. Summary 90
Chapter 4 More Moore’s Law 91
4 - 1. Design Introduction 93
4 - 2. Simulation methodology 96
4 - 3. Nanowire Device Design and performance projection 98
4 - 4. Analysis and Modeling for subthreshold kink 105
4 - 4 - 1. Evaluation of subthreshold kink for SOI nanowire MOSFETs 105
4 - 4 - 2. Impact of VDS and voltage scalability 113
4 - 4 - 3. Analytical modeling of subthreshold kink for SOI nanowire MOSFETs 114
4 - 5. Summary 120
Chapter 5 Conclusion 121
Summary this thesis 121
5 - 1. Future Work 122
5 - 1 - 1. Structure Design with Fins 123
Reference 127
Appendix - A 141
Appendix - B 152
參考文獻 References
[1] Intel Technology Node, Online: http://www.intel.com.tw/.
[2] International Technology Roadmap for Semiconductors, Online: http://public.itrs.net/.
[3] Yuan Taur and Tak H. Ning, 1998, Fundamentals of Modern VLSI Devices, New York.
[4] D. Hisamoto, W. C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T. J. King, J. Bokor, and C. Hu, “FinFET—A self-aligned double-gate MOSFET scalable to 20 nm,” IEEE Trans. Electron Devices, vol. 47, no. 12, pp. 2320-2325, December 2000.
[5] J. Hu, A. Nainani, Y. Sun, K. C. Saraswat, and H. S. P. Wong, “Impact of fixed charge on metal-insulator-semiconductor barrier height reduction,” Applied Physics Letters, vol. 99, no. 25, pp. 1-4, December 2011.
[6] B. Kim, D. I. Bae, P. Zeitzoff, X. Sun, T. E. Standaert, N. Tripathi, A. Scholze, P. J. Oldiges, D. Guo, H. Shang, and K. I. Seo, “Investigation of fixed oxide charge and fin profile effects on bulk FinFET device characteristics,” IEEE Electron Devices Letters, vol. 34, no. 12, pp. 1485-1487, December 2013.
[7] H. C. You, P. Y. Kuo, F. H. Ko, T. S. Chao, and T. F. Lei, “The impact of deep Ni salicidation and NH3 plasma treatment on nano-SOI FinFETs,” IEEE Electron Devices Letters, vol. 27, no. 10, pp. 799-801, October 2006.
[8] Sentaurus Device, User Guide, Synopsys Inc. ver. I-2013.12, December 2013.
[9] C. L. Lin, P. H. Hsiao, W. K. Yeh, H. W. Liu, S. R. Yang, Y. T. Chen, K. M. Chen, and W. S. Liao, “Effects of fin width on device performance and reliability of double-gate n-type FinFETs,” IEEE Trans. Electron Devices, vol. 60, no. 11, pp. 3639-3644, November 2013.
[10] J. Kedzierski, M. Ieong, E. Nowak, T. S. Kanarsky, Y. Zhang, R. Roy, D. Boyd, D. Fried, and H. S. P. Wong, “Extension and source/drain design for high-performance FinFET devices,” IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 952-958, April 2003.
[11] A. V. Y. Thean, Z. H. Shi, L. Mathew, T. Stephens, H. Desjardin, C. Parker, T. White, M. Stoker, L. Prabhu, R. Garcia, B. Y. Nguyen, S. Murphy, R. Rai, J. Conner, B. E. White, and S. Venkatesan, “Performance and variability comparisons between multi-gate FETs and planar SOI transistor,” in IEDM Tech. Dig., pp. 1-4, 2006.
[12] A. Asenov, “Random dopant induced threshold voltage lowering and fluctuations in sub-0.1μm MOSFET’s: a 3-d “Atomistic” simulation study,” IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 2505-2513, December 1998.
[13] N. Sano, K. Matsuzawa, M. Mukai, and N. Nakayama, “On discrete random dopant modeling in drift-diffusion simulation: physical meaning of ‘atomistic’ dopants,” Microelectronics Reliability, vol. 42, no. 2, pp. 189-199, February 2002.
[14] Y. Li, C. H. Hwang, T. Y. Li, and M. H. Han, “Process-variation effect, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies,” IEEE Trans. Electron Devices, vol. 57, no. 2, pp. 437-447, February 2010.
[15] P. Magnone, A. Mercha, V. Subramanian, P. Parvais, N. Collaert, M. Dehan, S. Decoutere, G. Groeseneken, J. Benson, T. Merelle, R. J. P. Lander, F. Crupi, and C. Pace, “Matching performance of FinFET devices with fin widths down to 10 nm,” IEEE Electron Device Letters, vol. 30, no. 12, pp. 1374-1376, December 2009.
[16] P. Magnone, F. Crupi, A. Mercha, P. Andricciola, H. Tuinhout, and R. J. P. Lander, “FinFET mismatch in subthreshold region: theory and experiments,” IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2848-2856, November 2010.
[17] N. Xu, F. Andrieu, B. Ho, B.-Y. Nguyen, O. Weber, C. Mazuré, O. Faynot, T. Poiroux, and T.-J. K. Liu, “Impact of back biasing on carrier transport in ultra thin-body and BOX (UTBB) fully depleted SOI MOSFETs,” in Proc. Symp. VLSI Tech., pp. 113-114, 2012.
[18] E. Baravelli, M. Jurczak, N. Speciale, K. D. Meyer and A. Dixit, “Impact of LER and random dopant fluctuations on FinFET matching performance,” IEEE Trans. on Nanotechnology, vol. 7, no. 3, pp. 291-298, May 2008.
[19] F. A. Lema, X. Wang, S. M. Amoroso, C. Riddet, B. Cheng, L. Shifren, R. Aitken, S. Sinha, G. Yeric, and A. Asenov, “Performance and variability of doped multithreshold FinFETs for 10-nm CMOS,” IEEE Trans. Electron Devices, vol. 61, no. 10, pp. 3372-3378, October 2014.
[20] P. Yao, R Trihy, J. Ge, K. Breen, and T. McConaghy, “Understanding and designing for variation in GLOBALFOUNDRIES 28 nm technology,” Proceedings of Design Automation Conference, User Track, June 2012.
[21] T. McConaghy, K. Breen, J. Dyck, and A. Gupta, Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide, pp. 67-68, Springer, New York, 2013.
[22] Z. Song, Z. Chen, A. Z. Yong, Y. Song, J. Wu, and K. Chien, “The failure mechanism worst stress condition for hot carrier injection of NMOS,” ECS Trans., vol. 52, no. 1, pp. 947-952, March 2013.
[23] W. S. Lau, “An extended unified schottky-poole-frenkel theory to explain the current-voltage characteristics of thin film metal-insulator-metal capacitors with examples for various high-k dielectric materials,” ECS Solid State Sci., vol. 1, no. 6, pp. N139-N148, May 2012.
[24] J.-Y. Cheng, C. W. Yeung, and C. Hu, “Extraction of front and buried oxide interface trap densities in fully depleted silicon-on-insulator metal oxide-semiconductor field-effect transistor,” ECS Solid State Letters, vol. 2, no. 5, pp. Q32-Q34 , February 2013.
[25] H. -W. Cheng, F. -H. Li, M.-H. Han, C.-Y. Yiu, C.-H. Yu, K.-F. Lee, and Y. Li, “3D device simulation of work function and interface trap fluctuations on high-κ / metal gate devices,” in IEDM Tech. Dig., pp. 379-382, 2010.
[26] C. Y. Chen, J. T. Lin, M. H. Chiang, and W. C. Hsu, “A steep subthreshold swing technique for gate-all-around SOI MOSFETs,” ECS Trans., vol. 66, no. 5, pp. 87-92, May 2015.
[27] S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, J. K. Ha, H. Lim, H. W. Park, D. W. Kim, T. Chung, K. Seok, and W. S. Lee, “Characteristics of sub 5nm tri-gate nanowire MOSFETs with single and poly si channels in SOI structure,” in Proc. Symp. VLSI Tech., pp. 142-143, 2009.
[28] P. Hashemi, L. Gomez, and J. L. Hoyt, “Gate-all-around n-MOSFETs with uniaxial tensile strain-induced performance enhancement scalable to sub-10-nm nanowire diameter,” IEEE Trans. Electron Devices, vol. 30, no. 4, pp. 401-403, April 2009.
[29] M. Li, K. H. Yeo, S. D. Suk, Y.Y. Yeoh, D. W. Kim, T. Y. Chung, K. S. Oh and W. S. Lee, “Sub-10 nm gate-all-around CMOS nanowire transistors on bulk si substrate,” in Proc. Symp. VLSI Tech., pp. 94-95, 2009.
[30] Y. Jiang, T. Y. Liow, N. Singh, L. H. Tan, G. Q. Lo, D. S. H. Chan and D. L. Kwong, “Nanowire FETs for low power CMOS applications featuring novel gate-all-around single metal FUSI gates with dual Φm and vt tune-ability,” in IEDM Tech. Dig., pp. 1-4, 2009.
[31] S. D. Suk, K. H. Yeo, K. H. Cho, M. Li, Y. Y. Yeoh, S. Y. Lee, S. M. Kim, E. J. Yoon, M. S. Kim, C. W. Oh, S. H. Kim, D. W. Kim and D. Park, “High-performance twin silicon nanowire MOSFET (TSNWFET) on bulk si wafer,” IEEE Trans. on Nanotechnology, vol. 7, no. 2, pp. 181-184, March 2008.
[32] Y. Jiang, T. Y. Liow, N. Singh, L. H. Tan, G.Q. Lo, D. S. H. Chan and D. L. Kwong, “Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire,” in Proc. Symp. VLSI Tech., pp. 34-35, 2008.
[33] N. Singh, A. Agarwal, L. K. Bera, T. L. Liow, R. Yang, S. C. Rustagi, C. H. Tung, R. Kumar, G. Q. Lo, N. Balasubramanian and D. L. Kwong, “High-performance fully depleted silicon nanowire (diameter ≤5nm) gate-all-around CMOS devices,” IEEE Trans. Electron Devices Letters, vol. 27, no. 5, pp. 383-386, May 2006.
[34] K. H. Yeo, S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Cho, K. H. Hong, S. Yun, M. S. Lee, N. Cho, K. Lee, D. Hwang, B. Park, D. W. Kim D. Park and B. I. Ryu, “Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius,” in IEDM Tech. Dig., pp. 1-4, 2006.
[35] C. Y. Chen, Y. B. Liao, and M. H. Chang, “Scaling study of nanowire and multi-gate MOSFETs,” IEEE Solid-State and Integrated-Circuit Technology Conf., pp. 57-60, 2008.
[36] C. Y. Chen, Y. B. Liao, M. H. Chang, K. Kim, W. C. Hsu and S. Y. Chang, “Optimal design and performance assessment of extremely-scaled si nanowire FET on insulator,” IEEE SOI Conf., pp. 1-2, 2009.
[37] X. Huang, W. C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y. K. Choi, K. Asano, V. Subramanian, T. J. King, J. Boker, and C. Hu, “Sub 50-nm FinFET: PMOS,” in IEDM Tech. Dig., pp. 67-70, 1999.
[38] N. Lindert, L. Chang, Y. K. Choi, E. H. Anderson, W. C. Lee, T. J. King, J. Bokor, and C. Hu, “Sub-60-nm quasi-planar FinFETs fabricated using a simplified process,” IEEE Electron Devices Letters, vol. 22, no. 10, pp. 487-489, October 2001.
[39] Taurus-Device ver: X-2005.10, User Guide Synopsys Inc., Oct. 2005.
[40] C. Lombardi, S. Manzini, A. Saporto, and M. Vanzi, “A physically based mobility model for numerical simulation of nonplanar devices,” IEEE Trans. on Computer Aided Design, vol. 7, no. 11, pp. 1164-1171, November 1988.
[41] M. H. Na, E. J. Nowak, W. Haensch, and J. Cai, “The effective drive current in CMOS inverters,” in IEDM Tech. Dig., pp. 121-124, 2002.
[42] J. Deng, and H. -S. P. Wong, “Metrics for performance benchmarking of nanoscale si and carbon nanotube FETs including device nonidealities,” IEEE Trans. Electron Devices, vol. 53, no. 6, pp. 401-403, June 2006.
[43] S. D. Suk, M. Li, Y. Y. Yeoh, K. H. Yeo, K. H. Cho, I. K. Ku, H. Cho, W. J. Jang, D. W. Kim, D. Park, and W. S. Lee, “Investigation of nanowire size dependency on TSNWFET,” in IEDM Tech. Dig., pp. 891-894, 2007.
[44] I. M. T. Luna, J. B. Rodan, F. G. Ruiz, C. M. Blanque, and F. Gamiz, “An analytical mobility model for square gate-all-around MOSFETs,” Solid-State Electronics vol. 90, pp. 18-22, March 2013.
[45] M. A. Khayer, and R. K. Lake, “Diameter dependent performance of high-speed, low-power InAs nanowire field-effect transistors,” Journal of Applied Physics, vol. 107, no. 1, pp.014502-1 - 014502-7, January 2010.
[46] J. T. Lin, C. Y. Chen, and M. H. Chang, “Pragmatic study of the nanowire FETs with nonideal gate structures,” IEEE Silicon Nanoelectronics Workshop Conf., pp. 1-2, 2010.
[47] Y. B. Liao, M. H. Chiang, Y. S. Lai, and W. C. Hsu, “A pragmatic design methodology using proper isolation and doping for bulk FinFETs,” Solid-State Electronics, vol. 85, pp. 45-53, July 2013.
[48] K. Shimizu, T. Saraya, and T. Hiramoto, “Suppression of electron mobility degradation in (100)-oriented double-gate ultrathin body nMOSFETs,” IEEE Electron Devices Letters, vol. 31, no. 4, pp. 284-286, April 2010.
[49] A. Afzalian, C. -W. Lee, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Quantum confinement effects in capacitance behavior of multigate silicon nanowire MOSFETs,” IEEE Trans. on Nanotechnology, vol. 10, no. 2, pp. 300-309, March 2011.
[50] R. Granzner, S. Thiele, C. Schippel, and F. Schwierz, “Quantum effects on the gate capacitance of trigate SOI MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 12, pp. 3231-3238, December 2010.
[51] K. Majumdar, N. Bhat, P. Majhi, and R. Jammy, “Effects of parasitics and interface traps on ballistic nanowire FET in the ultimate quantum capacitance limit,” IEEE Trans. Electron Devices, vol. 57, no. 9, pp. 2264-2273, September 2010.
[52] J. Zou, Q. Xu, J. Luo, R. Wang, R. Huang, and Y. Wang, “Predictive 3-D modeling of parasitic gate capacitance in gate-all-around cylindrical silicon nanowire MOSFETs,” IEEE Trans. Electron Devices, vol. 58, no. 10, pp. 3379-3387, October 2011.
[53] D. J. Frank, Y. Taur, M. Ieong, and H. S. P. Wong, “Monte carlo modeling of threshold variation due to dopant fluctuations,” in Proc. Symp. VLSI Tech., pp. 169-170, 1999.
[54] P. A Stolk, F. P. Widdershoven, and D. B. M. Klaassen, “Modeling statistical dopant fluctuations in MOS transistors,” IEEE Trans. Electron Devices, vol. 45, no. 9, pp. 1960-1971, September 1998.
[55] H. S. Wong, and Y. Taur, “Three-dimensional “Atomistic” simulation of discrete random dopant distribution effects sub-0.1μm MOSFET's,” in IEDM Tech. Dig., pp. 705-708, 1993.
[56] A. Asenov, and S. Saini, “Suppression of random dopant-induced threshold voltage fluctuations in sub-0.1-μm MOSFET’s with epitaxial and-doped channels,” IEEE Trans. Electron Devices, vol. 46, no. 8, pp. 1718-1724, December 1999.
[57] A. Asenov, G. Slavcheva, A. R. Brown, J. H. Davies, and S. Saini, “Increase in the random dopant induced threshold fluctuations and lowering in sub-100 nm MOSFETs due to quantum effects: a 3-D density-gradient simulation study,” IEEE Trans. Electron Devices, vol. 48, no. 4, pp. 722-729, April 2001.
[58] I. D. Mayergoyz, and P. Andrei, “Statistical analysis of semiconductor devices,” Journal of Applied Physics, vol. 90, no. 6, pp. 3019-3029, September 2001.
[59] P. Andrei, and I. Mayergoyz, “Quantum mechanical effects on random oxide thickness and random doping induced fluctuations in ultrasmall semiconductor devices,” Journal of Applied Physics, vol. 94, no. 11, pp. 7163-7172, December 2003.
[60] S. Roy, and A. Asenov, “Where do the dopants go?,” Science, vol. 309, no. 5733, pp. 388-390, July 2005.
[61] M. Aldegunde, A. Martinez, and A. Asenov, “Non-equilibrium green’s function analysis of cross section and channel length dependence of phonon scattering and its impact on the performance of Si nanowire field effect transistors,” Journal of Applied Physics, vol. 110, no. 9, pp. 094518-1 - 094518-9, November 2011.
[62] J. Song, B. Yu, Y. Yuan, and Y. Taur, “A review on compact modeling of multiple-gate MOSFETs,” IEEE Trans. Circuits and Systems, vol. 56, no. 8, pp. 437-447, August 2009.
[63] X. Tang, V. K. De, and J. D. Meindl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. Very Large Scale integration, vol. 5, no. 4, pp. 437-447, December 1997.
[64] S. Mudanai, W. K. Shih, R. Rios, X. Xi, J. H. Rhew, K. Kuhn, and P. Packan, “Analytical modeling of output conductance in long-channel halo-doped MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2091-2097, December 2006.
[65] M. H. Chiang, J. N. Lin, K. Kim, and C. T. Chunag, “Random dopant fluctuation in limited-width FinFET technologies,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2055-2059, August 2007.
[66] P. Singh, N. Singh, J. Miao W. T. Park, and D. L. Kwong, “Gate-all-around junctionless nanowire MOSFET with improved low-frequency noise behavior,” IEEE Electron Devices Letters, vol. 32, no. 12, pp. 1752-1754, December 2011.
[67] J. W. Yang, and J. G. Fossume, “On the feasibility of nanoscale triple-gate CMOS transistors,” IEEE Trans. Electron Devices, vol. 52, no. 6, pp. 1159-1164, June 2005.
[68] J. P. Colinge, C. W. Lee, A. Afzalian, N. D. Akhavan, R. Y. L. Ferain, P. Razavi, B. O’Nell, M. White, A. M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nature Nanotechnology, vol. 5, no. 3, pp. 225-229, February 2010.
[69] R. T. Doria, M. A. Pavanello, R. D. Trevsoli, M. D. Souza, C. W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. Kranti, and J. P. Colinge, “Analog operation of junctionless transistors at cryogenic temperatures,” IEEE SOI Conf., pp. 1-2, 2010.
[70] L. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junctionless multigate field-effect transistor,” Journal of Applied Physics, vol. 94, no. 5, pp.053511-1 - 053511-2, February 2009.
[71] L. W. Lee, A. N. Nazarow, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, R. T. Doria, and J. P. Colinge, “Low subthreshold slope in junctionless multigate transistors,” Journal of Applied Physics, vol. 96, no. 10, pp. 102106-1 - 102106-3, March 2010.
[72] J. P. Colinge, C. W. Lee, I. Ferain, N. D. Akhavan, R. Yan, P. Razavi, R. Yu, A. N. Nazarow, and Rodrigo T. Doria, “Reduced electric field in junctionless transistors,” Journal of Applied Physics, vol. 96, no. 7, pp. 073510-1 - 073510-3, February 2010.
[73] C. W. Lee, A. Borne, I. Ferain, A. Afzalian, R. Yan, N. D. Akhavan, P. Razavi, and J. P. Colinge, “High-temperature performance of silicon junctionless MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 3, pp. 620-625, March 2010.
[74] E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Effective mobility in nanowire FETs under quasi-ballistic conditions,” IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 336-344, January 2010.
[75] S. Migita, Y. Morita, M. Masahara, and H. Ota, “Electrical performances of junctionless-FETs at the scaling limit (LCH = 3 nm),” in IEDM Tech. Dig., pp. 1-4, 2012.
[76] Y. Li, C. H. Hwang, T. Y. Li, and M. H. Han, “Process-variation effect, metal-gate work-function fluctuation, and random-dopant fluctuation in emerging CMOS technologies,” IEEE Trans. Electron Devices, vol. 57, no. 2, pp. 437-447, February 2010.
[77] G. Giusi, and A. Lucibello, “Variability of the drain current in junctionless nanotransistors induced by random dopant fluctuation,” IEEE Trans. Electron Devices, vol. 61, no. 3, pp. 702-706, March 2014.
[78] V. P. Georgiev, E. A. Towie, and A. Asenov, “Impact of precisely positioned dopants on the performance of an ultimate silicon nanowire transistor: A full three-dimensional NEGF simulation study,” IEEE Trans. Electron Devices, vol. 45, no. 12, pp. 965-971, Mar. 2013.
[79] S. Markov, B. Cheng, and A. Asenov, “Statistical variability in fully depleted SOI MOSFETs due to random dopant fluctuations in the source and drain extensions,” IEEE Electron Device Letters, vol. 33, no. 3, pp. 315-317, Mar. 2012.
[80] X. Tang, V. K. De, and J. D. Meinl, “Intrinsic MOSFET parameter fluctuations due to random dopant placement,” IEEE Trans. Very Large Scale Integration System, vol. 5, no. 4, pp. 369-376, December 1997.
[81] S. Mudanai, W. K. Shih, R. Rios, X. Xi, J. H. Rhew, K. Kuhy, and P. Packan, “Analytical modeling of output conductance in long-channel halo-doped MOSFETs,” IEEE Trans. Electron Devices, vol. 53, no. 9, pp. 2091-2097, September 2006.
[82] J. P. Duarte, M. S. Kim, S. J. Choi, and Y. K. Choi, “A compact model of quantum electron density at the subthreshold region for double-gate junctionless transistors,” IEEE Trans. Electron Devices, vol. 59, no. 4, pp. 1008-1012, April 2012.
[83] J. P. Duarte, S. J. Choi, and Y. K. Choi, “A full-range drain current model for double-gate junctionless transistors,” IEEE Trans. Electron Devices, vol. 58, no. 12, pp. 4219-4225, December 2011.
[84] C. Y. Chen, J. T. Lin, and M. H. Chiang, “Comparative study of process variations in junctionless and conventional double-gate MOSFETs,” IEEE Nanotechnology Material and Device Conf., pp. 81-83, 2013.
[85] S. M. Nawaz, S. Dutta, A. Chattopahyay, and A. Mallik, “Comparison of random dopant and gate-metal workfunction variability between junctionless and conventional FinFETs,” IEEE Electron Devices Letters, vol. 35, no. 6, pp. 663-665, June 2014.
[86] C. Y. Chen, J. T. Lin, and M. H. Chiang, “High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application,” IEEE SOI Conf., pp. 1-2, 2010.
[87] Tohru Mogami, “Challenges for sub-10 nm CMOS devices,” IEEE ICSICT Conf., pp. 23-26, 2006.
[88] S. Takagi, and M. Takenaka, “High mobility material channel CMOS technologies based on heterogeneous integration,” IEEE International Workshop on Junction Technology Conf., pp. 1-6, 2011.
[89] J. G. Fossum, S. Krishnan, O. Faynot, S. Cristoloveanu, and C. Raynaud, “Subthreshold kinks in fully depleted SOI MOSFET’s,” IEEE Electron Devices Letters, vol. 16, no. 12, pp. 542-544, December 1995.
[90] J. T. Lin, H. H. Chen, K. Y. Lu, C. H. Sun, Y. C. Eng, C. H. Kuo, P. H. Lin, T. Y. Lai, and F. L. Yang, “Design theory and fabrication process of 90nm Unipolar-CMOS,” IEEE SNW Conf., pp. 1-2, 2010.
[91] N. N. Mojumder, and K. Roy, “Band-to-band tunneling ballistic nanowire FET: circuit-compatible device modeling and design of ultra-low-power digital circuits and memories,” IEEE Trans. Electron Devices, vol. 56, no. 10, pp. 2193-2201, October 2009.
[92] K. H. Kao, A. S. Verhulst, R. Rooyackers, B. Douhard, J. Delmotte, H. Bender, O. Richard, W. Vandervorst, E. Simoen, A. Hikavyy, R. Loo, K. Arstila, N. Collaert, A. Thean, M. M. Heyns, and K. D. Meyer, “Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors” Journal of Applied Physics, vol. 116, no. 21, pp. 214506-1 - 214506-11, December 2014.
[93] W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec” IEEE Electron Device Letters, vol. 28, no. 8, pp. 743-745, August 2007.
[94] C. Charbuillet, E. Dubois, S. Monfray, P. Bouillon, and T. Skotnicki, “Fabrication and analysis of CMOS fully-compatible high conductance impact-ionization MOS (I-MOS) transistors,” Int. ESSDERC Conf., pp. 299-302, 2006.
[95] P. G. Chen, Y. T. Wei, and M. H. Lee, “Experimental demonstration of ferroelectric gate-stack AlGaN/GaN-on-Si MOS-HEMTs with voltage amplification for power applications,” IEEE Trans. Electron Devices, vol. 61, no. 8, pp. 3014-3017, August 2014.
[96] M. H. Lee, Y. T. Wei, J. C. Lin, C. W. Chen, W. H. Tu, and M. Tang, “Ferroelectric gate tunnel field-effect transistors with low-power steep turn-on” AIP Advance, vol. 4, no. 10, pp. 107117-1 - 107117-6, October 2014.
[97] Y. B. Liao, M. H. Chiang, and W.-C. Hsu, “Performance evaluation of stacked gate-all-around MOSFETs,” Proc. EuroSOI, pp. 1-2, 2014.
[98] C. Shen, J. Q. Lin, E. H. Toh, K. F. Chang, P. Bai, C. H. Heng, G. S. Samudra and Y. C. Yeo. “On the performance limit of impact-ionization transistors,” in IEDM Tech. Dig., pp. 117-120, 2007.
[99] K. Gopalakrishnan, P. B. Griffin, and J. D. Plummer, “I-MOS: a novel semiconductor device with a subthreshold slope lower than KT/q” in IEDM Tech. Dig., pp. 289-292, 2002.
[100] E. H. Toh, G. H. Wang, L. Chan, G. Q. Lo, G. Samudra, and Y. C. Yeo, “Strain and materials engineering for the I-MOS transistor with an elevated impact-ionization region” IEEE Trans. Electron Device, vol. 54, no. 10, pp. 2778-2785, October 2007.
[101] D. Suh, and J. G. Fossum, “A physical charge-based model for non-fully depleted SOI MOSFET’s and its use in assessing floating-body effects in SO1 CMOS circuits,” IEEE Trans. Electron Devices, vol. 42, no. 4, pp. 728-737, April 1995.
[102] T. K. Suzuki, and T. Sugii, “Scaling-parameter-dependent model for subthreshold swing S in double-gate SOI MOSFETs” IEEE Electron Device Letters, vol. 15, no. 11, pp. 466-468, November 1994.
[103] C. P. Auth, and J. D. Plummer, “Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFETs” IEEE Electron Device Letters, vol. 18, no. 2, pp. 74-76, February 1997.
[104] Y. Okuto, and C. R. Crowell, “Threshold energy effect on avalanche breakdown voltage in semiconductor junctions,” Solid-State Electronics, vol. 18, no. 2, pp.161-168, July 1975.
[105] C. Y. Chen, J. T. Lin, and M. H. Chiang, “Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors,” Solid-State Electronics, vol. 92, pp. 57-62, February 2014.
[106] S. Veerarghavan, and J. G. Fossum, “A physical short-channel model for the thin-film SOI MOSFET application to device and circuit CAD” IEEE Trans. Electron Device, vol. 35, no. 11, pp. 1866-1875, November 1988.
[107] J. W. Yang, and J. G. Fossum, “On the feasibility of nanoscale triple-gate CMOS transistors” IEEE Trans. Electron Device, vol. 52, no. 6, pp. 1159-1164, June 2005.
[108] L. Chang, M. Ieong, and M. Yang, “CMOS circuit performance enhancement by surface orientation optimization,” IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1621-1627, October 2004.
[109] M. Yokiyama, Y. Urabe, T. Yasuda, H. Ishii, and N. Miyata, “High mobility III-V-on-insulator MOSFETs on si with ALD-Al2O3 box layer,” in Proc. Symp. VLSI Tech., pp. 235-236, 2010.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:自定論文開放時間 user define
開放時間 Available:
校內 Campus: 已公開 available
校外 Off-campus: 已公開 available


紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code