本論文提出了一些新的高速運算元件之設計與分析，主要的貢獻在於快速CORDIC(COordinate Rotation DIgital Computer)之旋轉架構設計上以及乘法器相關的研究。在快速旋轉架構的設計方面，我們提出了一個快速的旋轉架構可以減少平均的迴圈數為原來的一半。最近，更提出了一個新的平行化CORDIC旋轉演算法及其架構，與傳統的CORDIC演算法或先前的文獻相比較，具有省面積以及減少延遲時間的優點。
在快速平行乘法產生器的設計當中，我們提出了一個節省延遲時間的演算法來執行部份積的加總與最終加法器的分割，除了傳統的標準元件庫之外，也利用全客戶式設計進位儲存加法器來產生更快速的乘法器。在固定寬度乘法器的研究中，本論文提出了低誤差之無進位的固定寬度乘法器之設計，該乘法器的補償電路所需的成本極低，而且可以執行無進位的加法，它們的絕對平均誤差與變異數也比其他固定寬度乘法器小。

In this dissertation, the design and analysis of several fast arithmetic components are presented. Our contributions focus on the fast CORDIC rotation architectures and multipliers. In the CORDIC design, we proposed a fast rotation architecture that can reduce by half the average number of rotations. Furthermore, a new parallel CORDIC rotation algorithm and architecture (called para-CORDIC) is proposed that leads to smaller area and delay compared with the conventional CORDIC algorithm and previous works. In the design of the multiplier generator, a delay-efficient algorithm is used to perform the partial products summation and the final addition during the synthesis of fast parallel multipliers based on standard cell library or other full-custom circuit components. In the field of fixed-width multiplier designs, a lower-error fixed-width carry-free multiplier with low-cost compensation circuits is proposed that has smaller absolute average errors and variances compared with pervious methods.

Chapter 1 Introduction 1-1
Chapter 2 Fast CORDIC Architecture for Vector Rotation 2-1
2.1 Conventional CORDIC rotation algorithm 2-1
2.2 Derivation of a new CORDIC rotation algorithm 2-6
2.3 Summary 2-13
Chapter 3 Para-CORDIC: Parallel CORDIC Rotation Algorithm 3-1
3.1 Problem formulation 3-2
3.2 Para-CORDIC: Parallel CORDIC rotations 3-5
3.2.1 Binary to Bipolar Recoding (BBR) of 3-6
3.2.2 Micro-rotation Angle Recoding (MAR) algorithm and convergence proof 3-7
3.2.3 Para-CODIC algorithm and architecture 3-12
3.2.4 Mathematical derivation of the relationship between and 3-15
3.2.5 Extensions to the hyperbolic coordinate 3-17
3.3 Performance evaluation for Para-CORDIC 3-20
3.3.1 Evaluation of the z datapath 3-21
3.3.2 Evaluation of the X/Y datapath 3-23
3.4 Comparisons 3-25
3.5 Applications to Sine/Cosine function generations 3-30
3.6 Summary 3-33
Chapter 4 An Efficient Cell-Driven Multiplier Generator 4-1
4.1. Architecture of Parallel Multipliers 4-1
4.2 Delay optimization of the partial products compression 4-7
4.3 Partitioning for the final addition stage 4-13
4.3.1 Searching for the partition point between region 1 and region 2 4-15
4.3.2 Searching for the partition point between region 2 and region 3 4-15
4.4 Performance comparisons 4-18
4.5 Summary 4-23
Chapter 5 Low-Error Carry-Free Fixed-Width Multipliers Design 5-1
5.1 Problem formulation 5-2
5.2 Basic concept 5-3
5.3 Proposed fixed-width multipliers with simple compensation circuits 5-5
5.4 Error analysis and comparisons 5-9
5.4.1 Previous proposed fixed-width multipliers 5-9
5.4.2 Simulation results of error analysis 5-11
5.4.3 Area comparisons 5-12
5.5 Application to DCT/IDCT computations 5-14
5.6 Summary 5-17
Chapter 6 Conclusions and Future Works 6-1
Bibliography

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