對於在晶片匯流排的靈活、彈性，允許系統開發者可以選擇最理想架構，有效地滿足各種各樣的系統所需要的效能，是Reuse的關鍵所在。在晶片匯流排，AMBA是一個公開的標準，詳述組成一個系統的功能區塊相互連接和管理的機制，將使設計者在不須更改匯流排界面下，直接整合現有的IP核心將使得系統中的整體效益倍增。SoC設計者有時為了和周邊裝置匹配及頻寬，要在通道數和時脈頻率選擇一個最佳化的組合，因此選擇AMBA Multi-layer的架構。AMBA系統匯流排中AHB主要是針對高效率、高頻寬及快速系統模組所設計的匯流排，它可以連接如微處理器、晶片上或晶片外的記憶體模組和直接記憶體存取機制等高效率模組。它可以支援多個masters管理機制而達到最大的系統效能，是一個高速、高頻寬的匯流排。在本論文中，我們實作系統晶片匯流排基礎架構之自動化產生，它支援AMBA AHB、將系統頻寬最佳化的Multi-layer的AHB或是簡化成單一master的AHB-Lite架構。它都能根據使用者的設定來自動產生其匯流排的基礎架構。我們分別使用SDV和Synopsys所提供的AHB Monitor，來監測基礎匯流排的protocol是否符合規格。在Test Patterns方面，使用Bus Functional Model來對匯率排傳輸的各種情形做測試驗證。在硬體實作方面，我們使用SYS32TM、SYS32TME、SYS16TM和MEMCU來做三種AHB型式整合的例子。每一個例子也都做FPGA驗證及晶片實作，來證明匯流排基礎架構的可靠度。

For the on-chip bus, flexibility is the key to reuse by enabling developers to select the optimal architecture to efficiently meet the performance requirements of a wide variety of systems. AMBA is an open standard, on-chip bus specification that details a strategy for the interconnection and management of functional blocks that makes up a System-on-Chip (SoC). AMBA will let designers multiply the total bandwidth available in a system without changing the bus interface on existing intellectual property (IP) cores. Sometimes, the SoC designer to select the optimal combination of bus frequency (to match the peripherals) and number of channels (to achieve the bandwidth), using the AMBA Multi-layer architecture. The AHB of the AMBA System Bus connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory and interfaces. It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance. In this thesis, we implement an software, Automatic Generation of On-Chip Bus Infrastructure for SoC, and it supports the AMBA AHB, Multi-layer AHB architecture to optimize system bandwidth, or AHB-Lite to streamline single master layers. By user set up, it can generate the relative on-chip bus infrastructure. We use each AHB Monitor of SDV and Synposys to validate the protocol of infrastructure respectively. In Test Patterns, we use Bus Functional Model to verify all type transfers of bus. In hardware implement, we use SYS32TM, SYS32TME, SYS16TM, and MEMCU to integrate three type AHBs. Every example, we also build FPGA prototyping and chip layout. We do this to validate our on-chip bus infrastructure.

CHAPTER 1. 論文簡介 1
1.1 研究背景 1
1.2 研究動機 2
1.3 研究方法 3
1.4 主要貢獻 4
1-5 論文組織 5
CHAPTER 2. 相關研究 6
2.1 主要On-Chip Bus介紹 6
2.1.1 Crossbar Interconnect (Switch)簡介 6
2.1.2 AMBA (Advanced Microcontroller Bus Architecture)簡介 7
2.1.3 IBM CoreConnect Bus Architecture簡介 9
2.1.4 CoreFrame Architecture簡介 10
2.1.5 EC™ Interface簡介 11
2.1.6 Atlantic™ Interface簡介 12
2.1.7 Avalon™簡介 13
2.1.8 Silicore的WISHBONE Interconnect Bus簡介 14
2.1.9 IPBus™ (IDT Peripheral Bus) 簡介 15
2.1.10 SiliconBackplane™ Ⅲ MicroNetwork簡介 16
2.1.11 VSIA　(Virtual Socket Interface Alliance)簡介 17
2.1.12 Open Core Protocol簡介 18
2.2 各個OCB的比較 20
2.2.1 三態與多工器匯流排的比較 20
2.2.2 常見的On-Chip Bus比較 21
CHAPTER 3. AMBA架構分析 24
3.1 AMBA AHB 24
3.2 AMBA APB 25
3.3 AHB-Lite 26
3.4 Multi-layer AHB 28
3.5 AMBA AHB Operation 32
CHAPTER 4. 匯流排基礎架構之自動化產生 42
4.1 AMBA匯流排基礎模組 42
4.1.1 Arbiter 42
4.1.2 Decoder 43
4.1.3 Master to slave multiplexor 44
4.1.4 Slave to master multiplexor 45
4.1.5 Default slave 46
4.2 Automatic Generation of On-Chip Bus Infrastructure 46
4.2.1 以Script檔為基礎的產生器 46
4.2.2 以Form為基礎的產生器 48
4.3 Automatic Verification 50
4.3.1 Protocol驗證： 50
4.3.2 AHB Slave-side Monitor 51
4.3.3 Synopsys ACT 52
4.3.4 Bus Functional Model 53
CHAPTER 5. 系統單晶片整合實作及分析 57
5.1 各Master及Slave的IP核心 57
5.1.1 SYS32TDMI 57
5.1.2 SYS32TME 58
5.1.3 SYS16TM 59
5.1.4 MEMCU 59
5.1.5 UART 61
5.1.6 Interrupt Controller 61
5.1.7 Memory Controller 61
5.2 SoC Architecture 63
5.2.1 AHB-Lite: SYS32TM 63
5.2.2 AHB: SYS32TM 63
5.2.3 AHB-Lite: SYS16TM 64
5.2.4 Multi-layer AHB: SYS32TME 65
5.2.5 Multi-layer AHB: SYS32TME and Dual Port RAM 66
5.2.6 Multi-layer AHB: MEMCU 67
5.3 RTL驗證結果 67
5.3.1 Code Coverage 67
5.3.2 RTL Automatic Function Verification 68
5.3.3 Protocol Monitor 74
5.4 FPGA Prototyping 75
5.5 Cell-based Design 80
5.6 晶片實作 88
5.6.1 測試考量 91
CHAPTER 6. 結論與未來研究方向 95
6.1 結論 95
6.2 未來研究方向 95
參考文獻 (REFERENCES) 97
APPENDIX A ESLAB NLINT RULES 99

[1] Prakash Rashinkar, Peter Paterson, and Leena Signh, System-on-a-chip Verification: Methodology and Techniques, Kluwer Academic Publishers, 2001.
[2] M. Keating and P. Bricaud, Reuse Methodology Manual for System-on-a-Chip Designs, 3nd Edition, Kluwer Academic Publishers, 2002.
[3] Open SystemC Initiative. http://www.systemc.org/
[4] AMBA Specification, Rev. 2.0, ARM Inc, 1999.
http://www.arm.com/products/solutions/AMBA_Spec.html
[5] EC™ interface, v1.05, MIPS TECHNOLOGIES, 2002. http://www.mips.com/content/Documentation/MIPSDocumentation/BusSpecification/doclibrary
[6] CoreConnect Bus Architecture, White Paper, IBM Inc., 1999. http://www-3.ibm.com/chips/techlib/techlib.nsf/productfamilies/CoreConnect_Bus_Architecture
[7] WISHBONE Specification, Rev. B.2, Silicore Inc., Oct. 2001.
http://www.silicore.net/pdfiles/wishbone/specs/wbspec_b2.pdf
[8] Overview of the CoreFrame Architecture, Rev. 1.01, Palmchip Inc., Jan. 2002.
http://www.palmchip.com/coreframe_downloads.asp
[9] Virtual Socket On-chip Bus Attributes Specification, Rev. 0.9.6, VSIA Org., 1999.
http://www.vsi.org/resources/DataSheets.htm
[10] Atlantic Interface, Altera Corporation,
http://www.altera.com/products/ip/altera/t-alt-atlantic.html
[11] Avalon Bus Specification, Altera Corporation,
http://www.altera.com/literature/manual/mnl_avalon_bus.pdf
[12] IPBus™, Integrated Device Technology,
http://www.silicore.net/pdfiles/wishbone/misc/idtipbus.pdf
[13] SiliconBackplane III MicroNetwork, Sonics Inc.,
http://www.sonicsinc.com/sonics/products/siliconbackplaneIII/
[14] OCP Specification, OCP International Partnership, Release 1.0, http://www.ocpip.org/socket/ocpspec/
[15] AMBA AHB-Lite Overview, ARM Ltd., http://www.arm.com/miscPDFs/1744.pdf
[16] AMBA Multi-layer AHB Overview, ARM Ltd., http://www.arm.com/miscPDFs/1745.pdf
[17] AMBA AHB Cycle level Interface Specification, AHBCLI.1.1.0, ARM Ltd., July 2003, http://www.arm.com/products/solutions/ahbcli.html
[18] ARM System-Level Modeling, ARM Ltd., June 2003, http://www.arm.com/pdfs/Models_White_Paper.pdf
[19] Jindal, R. Jain, K., “Verification of transaction-level SystemC models using RTL testbenches,” Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design, pp. 199-203, June 2003.
[20] 資策會資訊市場情報中心, http://mic.iii.org.tw/intelligence/
[21] 新華電腦, http://www.microtime.com.tw/
[22] 陳信明, “微處理器之仿真器的軟硬體設計方法,” 碩士論文, 國立中山大學資訊工程學系, 2001.
[23] 宋裕文, “ARM微處理器硬體架構特色之微架構評估與改善,” 碩士論文, 國立中山大學資訊工程學系, 2003.
[24] 賴奇劭, “ARM7微處理器之衍生架構,” 碩士論文, 國立中山大學資訊工程學系, 2001.
[25] 王淳佑, “適用於低功率低成本資訊家電之16-bit微處理器,” 碩士論文, 國立中山大學資訊工程學系, 2002.
[26] 王威程, “以前瞻微處理器匯流排架構平台為基礎的嵌入式系統發展環境,” 碩士論文, 國立中山大學資訊工程學系, 2002.
[27] Structured Design Verification, Inc., http://www.sdvinc.com/
[28] 黃文凱, “適用於低成本嵌入式應用之多媒體微控制器,” 碩士論文, 國立中山大學資訊工程學系, 2002.
[29] A. Sangiovanni-Vincentelli and G. Martin, “Platform-Based Design and Software Design Methodology for Enbedded Systems,” IEEE Design & Test of Computers, Vol. 18, pp. 23-33, Nov. 2001.
[30] Hattori, T., “Design methodology of low-power microprocessors,” Design Automation Conference, pp. 390-393, 2003.
[31] LEON/AMBA VHDL model description, Rev. 2.2, Gaisler Research Inc., Nov. 2000. http://www.estec.esa.nl/wsmwww/leon/leonvhdl-2.2.pdf
[32] Youngwoo Kim, Kyoung Park, and Myungjoon Kim, “AMBA based multiprocessor system,” Proceedings of International Symposium on System-on-Chip, pp. 41-42, 2003.
[33] Park, J.H., Kim, I.K., Kim, S.M., Park, S.M., Koo, B.T., Shin, K.S., Seo, K.B. and Cha, J.J., “MPEG-4 video codec on an ARM core and AMBA”, Proceedings of Workshop and Exhibition on MPEG-4, pp. 95-98, 2001.
[34] David Flynn, “AMBA: enabling reusable on-chip designs,” IEEE Micro, pp. 20-27, 1997.
[35] nLint Rule Category, NOVAS Software Inc, Aug. 2004. http://www.novas.com/Products/nLint/