在此論文中，我們深入研究新穎金氧半場效電晶體應用於65奈米世代以下時，其電性特性與可靠度。大致來說，可將本論文粗略的分成兩個部分，分別為應變矽通道技術與高介電係數絕緣層/金屬閘極堆疊。首先，我們提出一項產生應力的方法來研究應變矽通道內的載子傳輸特性，主要是利用外界機械應力彎曲矽基板，藉此產生通道內的壓縮/拉伸應力。當我們分別將壓縮與拉伸應力施加於n型與p型電晶體通道上時，其汲極電流與載子移動率都有明顯的上升。其機制主要歸因於應力造成的有效傳輸質量下降與減少能谷間散射機率。然而，我們發現外界應力卻加劇n型電晶體的熱載子劣化。因此，我們探討受應力對基底電流與碰撞游離率的影響。當施加的應力增加時，我們發現基底電流的上升不是因為汲極電流的增加，而是與碰撞游離率有強烈的相關。根據應力與載子移動率上升的機制，我們歸納熱載子效應的劣化主要是由於應力造成能帶窄化導致碰撞游離所需的能量下降。
近年來，在p型電晶體的負偏壓溫度不穩定性扮演著正常操作下的主要劣化機制。因此，我們接下來探討p型電晶體受到外界單軸拉伸/壓縮應力下的負偏壓溫度不穩定特性。結果顯示單軸壓縮應力不只能夠提升驅動電流，更可以有效降低負偏壓溫度不穩定的劣化程度。相反地，當施加拉伸應力時，其元件性能將下降而負偏壓溫度不穩定的劣化也會因此加劇。藉由量測通道電容與應力的關係，我們發現由通道電容計算得到的反轉層內電洞濃度會隨拉伸/壓縮應力而增加/減少。根據反應-擴散模型，介面缺陷的產生速率與反轉層內的電洞濃度存在著相互影響的關係。因此，當應力改變反轉層內的電洞濃度也間接的影響存在介面的電化學反應機率。此外，我們亦採用電荷汲取量測來分析受不同應力下元件的介面缺陷產生數量，其量測結果與起始電壓漂移的現象也相當一致，這意味著受應力下的負偏壓溫度不穩定劣化主要仍是由介面缺陷產生的多寡所主導。
我們也嘗試結合本質與外界機械硬力，分析受到雙軸壓縮應力下的電性特性。當我們施加外界壓縮應力於通道寬度時，源/汲極具矽鍺結構的p型電晶體的汲極電流與載子移動率都發生明顯的下降，其機制主要是歸因於室溫下的有效傳導質量上升。然而，元件效能卻隨著溫度的上升而產生完全相反的現象，其溫度分界點約在363K。藉由觀察受單軸與雙軸壓縮應力下的價電帶結構，我們發現當溫度升高時，此時載子具有較高的能量並經由能谷間散射躍升至高能階帶，因此高溫下的傳導機制主要是由高能階特性主導，而受到雙軸應力下之高能階則具有較單軸應力低的傳導質量。此外，我們亦以降溫量測的方式來證明我們提出的模型。當溫度由300K降至100K時，可發現載子移動率的劣化變得更加明顯，其原因主要是載子於低溫無法獲得足夠的能量，所以傳輸機制便被具有較高質量的最低能階所主導。
另一方面，當互補式金氧半場效電晶體微縮至65奈米以下時，二氧化矽絕緣層與多晶矽閘極卻因閘極漏電過大而無法繼續使用。因此，在本論文的第二部份，我們藉由多種量測方式，如電荷汲取、分離式電容-電壓、直流式與脈衝式量測來建立並分析具有氧化鉿絕緣層/氮化鈦閘極電晶體之電性特性與物理模型。首先我們發現當n型電晶體金屬閘極中的鈦含量增加時，臨界電壓會明顯地下降；相反地，p型電晶體的起始電壓則呈現增加的趨勢。藉由對平帶電壓的分析，可發現金屬功函數隨著鈦含量的增加而減少是造成臨界電壓下降的主因。另外，我們也觀察有效載子移動率隨溫度(100K~300K)改變的趨勢，其結果指出不論在n型或p型電晶體中，高介電係數絕緣層中的remote phonon scattering會隨著鈦含量減少而增加，此因素將造成移動率下降。然而，我們亦發現閘極漏電流與金屬閘極中的氮含量有相當強烈的關係。我們利用脈衝式量測證實高介電係數絕緣層內的缺陷會被氮所修復，所以由Frenkel- Poole機制主導的漏電路徑將會減少，因此造成閘極漏電下降。

In this thesis, we investigate the electrical properties and reliability of novel metal-oxide-semiconductor field-effect transistors (MOSFETs) for 65 nm technology node and below. Roughly, we divide the thesis into two parts, strained-silicon channel engineering and high-k/metal gate stacks respectively. Firstly, to study the influence of stress on carrier transport properties, we proposed an approach to get uniaxial compressive/tensile stress from the channel by bending silicon substrate to enhance device performance. By applying uniaxial longitudinal tensile/compressive stress, the drain current and mobility were found to increase obviously in n/p-type MOSFETs, respectively. The enhancement can be attributed to the reduction of effective transport mass and to the suppression of inter-valley scattering. However, we found that the external mechanical stress aggravated hot carrier effects in n-type MOSFETs. Therefore, in n-type MOSFETs, the behaviors of the substrate current and the impact ionization rate under mechanical stress are investigated. It was found that the substrate current and gate voltage corresponding to the maximum impact ionization current has significantly increased by increasing external mechanical stress. According to the relationship to the strain-induced mobility enhancement, the increase in impact ionization efficiency resulted from the decrease in threshold energy for impact ionization which was due to the narrowing of the band gap.
In p-type MOSFETs, the reliability issue, named negative bias temperature instability, is the dominant degradation mechanism during ON-state operation. Therefore, we investigate the NBTI characteristics of strained p-type MOSFETs with external uniaxial tensile/compressive stress. The results indicate that uniaxial compressive stress not only enhances drive current but also reduces NBTI degradation. On the contrary, uniaxial tensile stress leads to a significant degradation in both of drive current and NBTI behavior. The observed Cgc-Vg curve shows the inversion capacitance is strongly dependent on mechanical strain, meaning that the probability of electrochemical reaction decreases/or increases due to the changes in inversion carrier density according to the Nit generation rate of the reaction-diffusion model. Moreover, the charge pumping result is also consistent with the threshold voltage shift of the strained device, which means the degradation is mainly due to trap generation at the Si/SiO2 interface.
In addition, to investigate the influences of biaxial compressive stress on p-MOSFETs, we attempts to combine intrinsic and external mechanical stress. It was found that drain current and hole mobility of p-type MOSFET with Si1-xGex raised Source/Drain and external applied mechanical stress significantly decreased due to the increase of effective conductive mass at room temperature. However, this phenomenon was inverted above 363K. Because hole can gain enough thermal energy to transit to higher energy level by inter-valley scattering, its transport mechanism was dominated by lower effective mass at higher energy level. Besides, the model is also evidenced that the mobility degradation under biaxial compressive stress becomes aggravated while temperature decreases from 300 K to 100 K, which is mainly due to the increase of the ratio of carriers occupied in lowest band.
On the other hand, the SiO2 dielectric and poly-gate are unsuitable for CMOS application below 65 nm technology node due to unacceptable gate leakage current. Therefore, in the second section of this thesis, we established the electrical characteristics and physical mechanisms of MOSFETs with HfO2 dielectric/TiN gate by analyzing experimental data from charge pumping, split C-V, DC Id-Vg, and pulse Id-Vg. It is found that the threshold voltage (Vth) has a significant decrease as titanium increases in metal gate for n-MOSFETs, whereas the Vth increases in p-MOSFETs. By examining flat band voltage, we found the Vth shift was resulted from metal gate work function (φm) which became smaller as titanium increased in metal gate. In addition,the dependence of effective mobility on temperature from 100K to 300K was entirely analyzed, which indicated HfO2 remote phonon scattering as the dominant cause of the mobility degradation in n- and p-type MOSFETs when titanium decreased.
However, the gate leakage current is also strongly dependent on the nitrogen in metal
gate. It is proved that the nitrogen can assivate the traps in HfO2 by pulse I-V,leading to the decrease in gate leakage dominated by Frenkel- Poole mechanism.

Abstract (Chinese) i
Abstract (English) iv
Contents viii
Fugure Captions xi
Table Captions xvi

Chapter 1 Introduction
1.1 General Background 1
1.1.1 Overview of Strained Silicon Channel
Engineering 2
1.1.2 Overview of High-k Insulator and Metal Gate
Electrode 4
1.2 Motivation 5
1.3 Outline of the thesis 6
Reference 8

Chapter 2 Parameter Extraction and Measurement Technique
2.1 Method of Device Parameter Extraction 16
2.2 Principle of Measurement Technique 18
2.2.1 Charge Pumping 18
2.2.2 Split C-V 20
2.2.3 Pulse I-V 23
Reference 25

Chapter 3 Substrate Current Enhancement in Strained n-MOSFETs
3.1 Introduction 36
3.2 Effects of Strain on the Conduction Band 39
3.3 Experiment 40
3.4 Results and Discussion 41
3.5 Summary 45
Reference 47

Chapter 4 Biaxial Strained Effects on Strained p-MOSFETs
4.1 Introduction 58
4.2 Effects of Strain on the Valence Band 59
4.3 Experiment 60
4.4 Results and Discussion 61
4.5 Summary 64
Reference 66

Chapter 5 NBTI Degradation in Strained p-MOSFETs
5.1 Introduction 74
5.2 Mechanism of Negative Bias Temperature
Instability 76
5.3 Experiment 78
5.4 Results and Discussion 79
5.5 Summary 82
Reference 84

Chapter 6 Impacts of TixN1-x on HK/MG MOSFETs
6.1 Introduction 93
6.2 Experiment 95
6.3 Results and Discussion 97
6.4 Summary 103
Reference 105

Chapter 7 Conclusion and Future Work
7.1 Summary of Experimental Works 121
7.2 Suggestions for Further Study 123

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